An electric component comprising a terminal electrode and a hot-melt polymer layer formed on the terminal electrode, wherein the hot-melt polymer layer comprises (i) 100 parts by weight of a metal powder and (ii) 1 to 30 parts by weight of a polymer, wherein melt mass-flow rate (MFR) of the polymer is 0.5 to 20 g/10 min. at 120 to 200 C. and 0.3 to 8 kgf.

The present invention provides a heat dissipative semiconductor package. The semiconductor package includes a package body in a flat rectangular shape. The semiconductor package further includes a die, a conductive block, multiple metal blocks, a molding layer, and a redistribution layer. A first contact of the die is electrically connected to a first pin. A second contact of the die is electrically connected to a second pin via the redistribution layer and the conductive block. The first pin and the second pin are respectively exposed from the bottom surface of the package body to curve, extend, and cover different side surfaces of the package body. The conductive block and the metal blocks are formed by dicing a same VCB. Heat generated by the die can be effectively dissipated externally through the first pin, the second pin, and the conductive block, and thus cooling the die.

A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallisation layer is formed on the second surface of the semiconductor substrate. The metallisation layer has a thickness which is greater than the device thickness.

A semiconductor package comprises two or more chips, a first molding layer, a second molding layer, a third molding layer, a fourth molding layer, a bottom redistribution layer (RDL), a middle RDL, and a top RDL. The two or more chips comprise a first chip and a second chip. The top RDL comprises a first copper plate and a second copper plate. A plurality of vias electrically connect the second copper plate to the second chip. A method comprises the steps of preparing two or more chips; forming a chip-level molding layer; forming a middle RDL; forming a lower-level molding layer; forming a bottom RDL; forming a lowest-level molding layer; forming a top RDL; and forming a top-level molding layer so as to fabricate a semiconductor package.