Disclosed are an array substrate, and a display device, and a method for manufacturing the same. The array substrate includes: a base substrate, and a thin film transistor, a planarization pattern, a bonding pattern, and a conductive structure that are disposed on the base substrate. The thin film transistor, the planarization pattern, and the bonding pattern are laminated in a direction going distally from the base substrate. The planarization pattern is provided with a via and a groove, the conductive structure is disposed in the via, wherein the bonding pattern is conductive and is electrically connected to the thin film transistor by the conductive structure, an orthographic projection of the bonding pattern on the base substrate falls outside an orthographic projection of the groove on the base substrate, and the groove is configured to accommodate an adhesive.

A printed circuit board includes: a first insulating layer; a first cavity disposed in one surface of the first insulating layer; a plurality of protrusion portions spaced apart from each other in the first cavity; and a first wiring layer embedded in the one surface of the first insulating layer.

A platform for hermetic heterogeneous integration of passive and active electronic components is provided herein. The platform can include a substrate that provides a hermetic electrical interconnection between integrated circuits and passive devices, such as resistors, capacitors, and inductors. Such substrates can be formed of a dielectric, such as a ceramic, and include electrical interconnects and can further include one or more passive devices. The substrate can include one or more cavities, at least a primary cavity dimensioned to receive an active device and one or more secondary cavities can be included for secondary connector pads for interfacing with the active and passive devices and which can be separately hermetically sealed. The substrate can include a multi-coil inductor defined within alternating layers of the substrate within sidewalls that surround the primary cavity to minimize size of the device package while optimizing the size of the coil.

A cathode configured for a solid-state battery includes a body having grains of inorganic material sintered to one another, wherein the grains comprise lithium. A thickness of the body is from 3 μm to 100 μm. The first major surface and the second major surface have an unpolished granular profile such that the profile includes grains protruding outward from the respective major surface with a height of at least 25 nm and no more than 150 μm relative to recessed portions of the respective major surface at boundaries between the respective grains.

A method of manufacturing a semiconductor integrated circuit includes a first ion implantation process implanting impurity ions of a second conductivity type into a bottom surface of a semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a first current suppression layer, and a second ion implantation process implanting impurity ions of a first conductivity type into the bottom surface of the semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a second current suppression layer. The semiconductor integrated circuit includes a first well region of the first conductivity type and a second well region of the second conductivity type provided in an upper portion of the first well region. The first current suppression layer is separated from the first well region and the second current suppression layer is provided under the first current suppression layer.

A method including followings is provided. An encapsulated device including a semiconductor die and an insulating encapsulation laterally encapsulating the semiconductor die is provided. An insulating layer is formed over a surface of the encapsulated device. A groove pattern is formed on the insulating layer. A conductive paste is filled in the groove pattern and the conductive paste filled in the groove pattern is cured.

A mass transfer device and a transfer method therefor are provided. The mass transfer device includes a transfer container. The transfer container is filled with insulating liquid and provided with two electrode plates. The two electrode plates are arranged opposite to each other and have opposite electrical polarities. One of the two electrode plates is provided with a second substrate on a surface of the electrode plate opposite to the other one of the two electrode plates. The second substrate is configured to hold transferred light-emitting diode (LED) chips. The transfer container is externally provided with a laser emitter. The laser emitter is aligned with LED chips on a first substrate. The first substrate is arranged between the two electrode plates and mounted on a first displacement device. The first displacement device is configured to control the first substrate to move vertically downward.

Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.

Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.

A method of manufacturing an electronic device includes providing a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer, and removing at least a portion of each of the two conductive layers to respectively form an antenna pattern and a circuit pattern of a chip package at the two opposite surfaces of the core dielectric layer.