A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

The present application provides a method for preparing a semiconductor package The method includes bonding a bottom device die onto a package substrate; attaching a top device die onto the bottom device die; attaching an additional package substrate onto the top device die; establishing electrical connection between the additional package substrate and the top device die, between the additional package substrate and the package substrate, and between the top device die and the package substrate; and encapsulating the bottom device die, the top device die and the additional package substrate by an encapsulant.

Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.

Several embodiments of microelectronic configurations with logic components and associated methods of manufacturing are disclosed herein. In one embodiment, the configuration includes a substrate with a recess, a first die carried by the substrate wherein the die substantially covers the recess, and a logic component carried by the die in a location exposed by the recess. The logic component can be substantially coplanar with the substrate. The die is electrically connected to a terminal on a one side of the substrate, and the logic component is electrically connected to a terminal on an opposite side of the substrate.

A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto.

A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto.

An epoxy resin composition for encapsulating a semiconductor device and a semiconductor device encapsulated by the epoxy resin composition, the composition including a base resin; a filler; a colorant; and a thermochromic pigment, wherein a color of the thermochromic pigment is irreversibly changed when a temperature thereof exceeds a predetermined temperature.

An epoxy resin composition for encapsulating a semiconductor device and a semiconductor device encapsulated by the epoxy resin composition, the composition including a base resin; a filler; a colorant; and a thermochromic pigment, wherein a color of the thermochromic pigment is irreversibly changed when a temperature thereof exceeds a predetermined temperature.

An ion trap apparatus (e.g., ion trap chip) having a plurality of electrodes is provided. The ion trap apparatus may comprise a plurality of interconnect layers, a substrate, and at least one integrated switching network layer disposed between the plurality of interconnect layers and the substrate. The integrated switching network layer may comprise a plurality of monolithically-integrated controls and/or switches configured to condition a voltage signal applied to at least one of the plurality of electrodes. An example ion trap apparatus may comprise a surface ion trap chip. The ion trap apparatus may be configured to operate within a cryogenic chamber.

A microelectronic package (10) can include lower and upper package faces (11, 12), lower terminals (25) at the lower package face, upper terminals (45) at the upper package face, first and second microelectronic elements (30) each having memory storage array function, and conductive interconnects (15) each electrically connecting at least one lower terminal with at least one upper terminal. The conductive interconnects (15) can include first conductive interconnects (15a) configured to carry address in formation, signal assignments of a first set (70a) of the first interconnects having (180) rotational symmetry about a theoretical rotational axis (29) with signal assignments of a second set (70b) of first interconnects. The conductive interconnects (15) can also include second conductive interconnects (15b) configured to carry data information, the position of each second conductive interconnect having (180) rotational symmetry about the rotational axis (29) with a position of a corresponding no-connect conductive interconnect (15d).