The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate. An isolation structure is arranged within the substrate and surrounds an upper surface of the substrate. The isolation structure includes one or more surfaces defining one or more trenches that are laterally between the isolation structure and the substrate. A conductive gate is over the substrate and laterally between a source region and a drain region disposed within the upper surface of the substrate. The conductive gate extends into the one or more trenches and has an upper surface that continuously extends past opposing sides of the one or more trenches.

The present disclosure provides a method of manufacturing a semiconductor device includes forming a first gate insulating film on a substrate for a first device, forming a first gate electrode on the first gate insulating film; forming a mask pattern on the first gate electrode to expose opposing end portions of the first gate electrode, wherein a length of the mask pattern is smaller than a length of the first gate electrode; performing ion implantation through the exposed opposing end portions of the first gate electrode using the mask pattern to simultaneously form first and second drift regions in the substrate; forming spacers on sidewalls of the first gate electrode, respectively; and forming a first source region and a first drain region in the first and second drift regions, respectively.

A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a plurality of floating gates, a tunneling dielectric layer, a plurality of control gates, and an ONO layer. The floating gates are located on the substrate, and the tunneling dielectric layer is located between the substrate and each of the floating gates. The control gates are located on the floating gates, and the ONO layer is located on two sidewalls of each of the control gates and between each of the control gates and each of the floating gates.

A MOS transistor is produced on and in an active zone and included a source region and a drain region. The active zone has a width measured transversely to a source-drain direction. A conductive gate region of the MOS transistor includes a central zone and, at a foot of the central zone, at least one stair that extends beyond the central zone along at least an entirety of the width of the active zone.

A method of fabricating a transistor structure with silicide layers includes providing a substrate. A gate structure is disposed on the substrate. Two composite spacers are respectively disposed at two sides of the gate structure. Later, two source/drain doping regions are respectively formed in the substrate at two sides of the gate structure. Then, a protective material layer is formed to cover the gate structure and the two composite spacers. Subsequently, the protective material layer is etched to form two protective layers contacting the substrate and respectively covering the two composite spacers. Next, a cleaning process is performed to clean the residues from etching the protective material layer. Finally, a silicide process is performed to form numerous silicide layers respectively disposed on the source/drain doping regions outside of the protective layers and on the gate structure.

After a MISFET is formed on a substrate including a semiconductor substrate, an insulating layer and a semiconductor layer, an interlayer insulating film and a first insulating film are formed on the substrate. Also, after an opening is formed in each of the first insulating film and the interlayer insulating film, a second insulating film is formed at each of a bottom portion of the opening and a side surface of the opening and also formed on an upper surface of the first insulating film. Further, each of the second insulating film formed at the bottom portion of the opening and the second insulating film formed on the upper surface of the first insulating film is removed by etching. After that, an inside of the opening is etched under a condition that each of the first insulating film and the second insulating film is less etched than the insulating layer.

The present disclosure provides a method of manufacturing a semiconductor device includes forming a first gate insulating film on a substrate for a first device, forming a first gate electrode on the first gate insulating film; forming a mask pattern on the first gate electrode to expose opposing end portions of the first gate electrode, wherein a length of the mask pattern is smaller than a length of the first gate electrode; performing ion implantation through the exposed opposing end portions of the first gate electrode using the mask pattern to simultaneously form first and second drift regions in the substrate; forming spacers on sidewalls of the first gate electrode, respectively; and forming a first source region and a first drain region in the first and second drift regions, respectively.

A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a plurality of floating gates, a tunneling dielectric layer, a plurality of control gates, and an ONO layer. The floating gates are located on the substrate, and the tunneling dielectric layer is located between the substrate and each of the floating gates. The control gates are located on the floating gates, and the ONO layer is located on two sidewalls of each of the control gates and between each of the control gates and each of the floating gates.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate having interior surfaces that define a trench within an upper surface of the substrate. One or more dielectric materials are disposed within the trench. A source region disposed within the substrate and a drain region is disposed within of the substrate and separated from the source region along a first direction. A gate structure is over the upper surface of the substrate between the source region and the drain region. The upper surface of the substrate has a first width directly below the gate structure that is larger than a second width of the upper surface of the substrate within the source region or the drain region. The first width and the second width are measured along a second direction that is perpendicular to the first direction.

Disclosed examples include LDMOS transistors and integrated circuits with a gate, a body region implanted in the substrate to provide a channel region under a portion of the gate, a source adjacent the channel region, a drain laterally spaced from a first side of the gate, a drift region including a first highly doped drift region portion, a low doped gap drift region above the first highly doped drift region portion, and a second highly doped region portion above the gap drift region, and an isolation structure extending through the second highly doped region portion into the gap drift region portion, with a first end proximate the drain region and a second end under the gate dielectric layer, where the body region includes a tapered side laterally spaced from the second end of the isolation structure to define a trapezoidal JFET region.