There is disclosed a method for manufacturing a MOSFET with lateral channel in SiC, said MOSFET comprising simultaneously formed n type regions (7) comprising an access region (7a) and a JFET region (7b) defining the length of the MOS channel (17), and wherein the access region (7a) and the JFET region (7b) are formed by ion implantation by using one masking step. The design is self-aligning so that the length of the MOS channel (17) is defined by simultaneous creating n-type regions on both sides of the channel (17) using one masking step. Any misalignment in the mask is moved to other less critical positions in the device. The risk of punch-through is decreased compared to the prior art. The current distribution becomes more homogenous. The short-circuit capability increases. There is lower Drain-Source specific on-resistance due to a reduced MOS channel resistance. There is a lower JFET resistance due to the possibility to increase the JFET region doping concentration.

A drift layer and a source region have a first conductivity type. A base region has a second conductivity type. A first trench penetrates the source region and the base region. A gate electrode is provided in the first trench through a gate insulation film. A first relaxation region is disposed below the first trench, and has the second conductivity type. A source pad electrode is electrically connected to the first relaxation region. A gate pad electrode is disposed in a non-element region. An impurity region is disposed in the non-element region, is provided on the drift layer, and has the first conductivity type. A second trench penetrates the impurity region. A second relaxation region is disposed below the second trench, and has the second conductivity type.

An object of the present invention is to provide a highly reliable semiconductor device by preventing precipitation of an oxide to prevent peeling of a resin layer. The semiconductor device includes: a resin layer provided so that at least a part of the resin layer extends on a front surface of a semiconductor layer on an outer peripheral side with respect to an outer peripheral end of a field insulating film; and a floating well region spaced apart from a termination well region in a surface layer of the semiconductor layer, the floating well region formed to be in contact with an outer peripheral end of the field insulating film to extend to the outer peripheral side with respect to the outer peripheral end of the field insulating film.

A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate electrode, a first electrode, and a gate electrode pad. A first lower region opposing the gate electrode pad in a depth direction has a carrier recombination rate that is lower than that of a second lower region opposing the first electrode in the depth direction. With such a configuration, when high electric potential is applied to a source electrode and a built-in PN diode is driven, the generation of crystal defects may be suppressed.

A method of manufacturing an insulated gate semiconductor device includes simultaneously forming a gate trench and a contact trench that respectively penetrate form a top of the electrode contact region through a main electrode contact region and a injection control region in a depth direction and respectively reach a charge transport region, the contact trench being disposed at a position laterally separated from the gate trench in a plan view; and embedding a gate electrode inside the gate trench with a gate insulating film interposed therebetween, thereby forming an insulated gate structure, and simultaneously embedding an injection suppression region inside the contact trench, the gate electrode and the injection suppression region being both made of a second semiconductor material having a narrower bandgap than a bandgap of the first semiconductor material of the charge transport region.

A power conversion circuit includes: a MOSFET having a super junction structure; an inductive load; and a freewheel diode. A switching frequency of the MOSFET is 10 kHz or more. When the MOSFET is turned off, a first period during which a drain current decreases, a second period during which the drain current increases, and a third period during which the drain current decreases again appear in this order. The freewheel diode is an Si-FRD or an SiC-SBD, and current density obtained by dividing a current value of the forward current by an area of an active region of the freewheel diode falls within a range of 200 A/cm.sup.2 to 400 A/cm.sup.2 when the freewheel diode is the Si-FRD, and the current density falls within a range of 400 A/cm.sup.2 to 1500 A/cm.sup.2 when the freewheel diode is the SiC-SBD.

An integrated circuit comprising a SGT MOSFET and a SBR is disclosed. The SBR horizontally disposed in different areas to the SGT MOSFET on single chip creates a low potential barrier for majority carrier in MOS channel, therefore has lower forward voltage and reverse leakage current than conventional Schottky Barrier Rectifier. Moreover, in some preferred embodiment, a MSO structure is applied to the shielded gate structure to further reduce the on-resistance.

In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.

Embodiments of SiC devices and corresponding methods of manufacture are provided. In some embodiments, the SiC device has shielding regions at the bottom of some gate trenches and non-linear junctions formed with the SiC material at the bottom of other gate trenches. In other embodiments, the SiC device has the shielding regions at the bottom of the gate trenches and arranged in rows which run in a direction transverse to a lengthwise extension of the trenches. In still other embodiments, the SiC device has the shielding regions and the non-linear junctions, and wherein the shielding regions are arranged in rows which run in a direction transverse to a lengthwise extension of the trenches.

Disclosed is a semiconductor device including a semiconductor layer having a main surface, a first conductivity type drift region formed at a surface layer part of the main surface, a super junction region having a first conductivity type first column region and a second conductivity type second column region, a second conductivity type low resistance region formed at the surface layer part of the drift region and having an impurity concentration in excess of that of the second column region, a region insulating layer formed on the main surface and covering the low resistance region such as to cause part of the low resistance region to be exposed, a first pad electrode formed on the region insulating layer such as to overlap with the low resistance region, and a second pad electrode formed on the main surface and electrically connected to the second column region and the low resistance region.