A MOSFET according to the present invention includes a semiconductor base substrate having a super junction structure. A gate electrode is on a first main surface side of the semiconductor base substrate byway of a gate insulation film, wherein in a state where a total amount of dopant in an n-type column region differs from a total amount of dopant in a p-type column region, assuming a depth position where an average positive charge density (x) becomes 0 as X.sub.m, assuming a deepest depth position of the surface of the depletion layer on the first main surface side as X.sub.0, assuming a depth position where the reference average positive charge density .sub.0(x) becomes 0 as X.sub.m, and assuming a deepest depth position of the depletion layer on the first main surface side as X.sub.0, a relationship of |X.sub.0X.sub.0|<|X.sub.mX.sub.m| is satisfied.

A semiconductor device has first second-conductivity-type high-concentration regions, second second-conductivity-type high-concentration regions, third second-conductivity-type high-concentration regions, and fourth second-conductivity-type high-concentration regions. The first connecting regions each connect a portion of each of the first second-conductivity-type high-concentration regions and a portion of each of the second second-conductivity-type high-concentration regions. The second connecting regions each connect a portion of each of the third second-conductivity-type high-concentration regions and a portion of each of the fourth second-conductivity-type high-concentration regions. A ratio of a mathematical area of the first connecting regions to a mathematical area of the second second-conductivity-type high-concentration regions is greater than a ratio of a mathematical area of the second connecting regions to a mathematical area of the fourth second-conductivity-type high-concentration regions.

According to one embodiment, a semiconductor device includes first and second electrodes, first, second, and third semiconductor regions, a gate electrode, first, and second conductive parts. The first semiconductor region includes a first region and a second region. The second semiconductor region is provided on the first region. The third semiconductor region is provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The gate electrode opposes the second semiconductor region in a second direction. The first conductive part is provided on the second region and is provided in a plurality in a third direction. The first conductive parts are arranged with the gate electrode in the second direction. The second conductive part is provided on the second region, and arranged with the gate electrode and the first conductive parts in the third direction.

A silicon carbide semiconductor substrate includes a first conductivity type substrate doped with a first conductivity type impurity to have a first conductivity type and having a specific resistance of 30 mcm or less. A lifetime of minority carriers in the first conductivity type substrate is set to 100 nsec or less.

A vertical-conduction MOSFET device, includes: a semiconductor body, having a front side and a back side and having a first conductivity; a trench-gate region; a body region, having the first conductivity; a source region, having a second conductivity; and a drain region, having the second conductivity. The source region, body region, and drain region are aligned with one another along a first direction and define a channel area, which, in a conduction state of the MOSFET device, hosts a conductive channel. The drain region borders on a portion of the semiconductor body having the first conductivity, thus forming a junction diode, which, in an inhibition state of the MOSFET device, is adapted to cause a leakage current to flow outside the channel area.

The object is to provide a semiconductor device that prevents a snapback operation and has excellent heat dissipation. The semiconductor device includes a semiconductor substrate, transistor portions, diode portions, a surface electrode, and external wiring. The transistor portions and the diode portions are provided in the semiconductor substrate and are arranged in one direction parallel with the surface of the semiconductor substrate. A bonding portion of the external wiring is connected to the surface electrode. The transistor portions and the diode portions are provided in a first region and a second region and alternately arranged in the one direction. A first transistor width and a first diode width in the first region are smaller than a width of the bonding portion. A second transistor width and a second diode width in the second region are larger than the width of the bonding portion.

The semiconductor device according to the present invention includes: a semiconductor layer made of SiC; an impurity region formed by doping the semiconductor layer with an impurity; and a contact wire formed on the semiconductor layer in contact with the impurity region, while the contact wire has a polysilicon layer in the portion in contact with the impurity region, and has a metal layer on the polysilicon layer.

A MOSFET includes: a semiconductor base substrate having n-type column regions and p-type column regions, the n-type column regions and the p-type column regions forming a super junction structure; and a gate electrode which is formed on a first main surface side of the semiconductor base substrate by way of a gate insulation film, wherein crystal defects whose density is increased locally as viewed along a depth direction are formed in the n-type column regions and the p-type column regions, using the first main surface as a reference and assuming a depth to a deepest portion of the super junction structure as Dp, a depth at which density of the crystal defects exhibits a maximum value as Dd, and a half value width of density distribution of the crystal defects as W, a relationship of 0.25DpDd<0.95Dp and a relationship of 0.05Dp<W<0.5Dp are satisfied.

A semiconductor device includes a semiconductor part including first to fifth layers; an electrode on a front surface of the semiconductor part; first and second control electrodes between the semiconductor part and the electrode. The first layer includes first and second portions alternately arranged along the front surface of the semiconductor part. The second layer is positioned between the first and second portions of the first layer. The first and second control electrodes are placed at boundaries of the first and second portions and the second layer, respectively. The third layer is provided between the second electrode and the first and second portions of the first layer. The fourth and fifth layers are selectively provided between the third layer and the second electrode. The first control electrode is opposed to the first, third and fourth layers. The second control electrode is opposed to the first, third and fifth layers.

In a transistor region of an active region, trench-gate MOS gates for a vertical MOSFET are formed on the front surface side of a semiconductor substrate. In a non-effective/pad region of the active region, a gate pad is formed on the front surface of the semiconductor substrate with an interlayer insulating film interposed therebetween. An n-type region is formed spanning across the entire non-effective region in the surface layer of the front surface of the semiconductor substrate. The portion directly beneath the gate pad is only an n-type region constituted by an n.sup.+ starting substrate, an n.sup. drift region, and the n-type region, with the interlayer insulating film sandwiched thereabove. No n.sup.+ source region is formed in a p-type base region extension which is the portion of a p-type base region that extends into the non-effective region.