A device includes a first transistor having a first source, a first gate, a first drain, and one or more electrodes. The first transistor serves as an inverter. The device also includes a second transistor having a second source, a second gate, and a second drain. The first and second sources are connected together. The first and second drains are connected together. The second transistor serves as an output, a driver, or both. The one or more electrodes, the second gate, or a combination thereof serve as tapped drains that are configured to sample a stepped voltage of the second transistor.

The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.

An active matrix substrate of an embodiment of the present invention includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate. Each oxide semiconductor TFT includes a lower gate electrode provided on the substrate, a gate insulating layer covering the lower gate electrode, an oxide semiconductor layer provided on the gate insulating layer, a source electrode which is in contact with the source contact region of the oxide semiconductor layer, a drain electrode which is in contact with the drain contact region of the oxide semiconductor layer, an insulating layer covering the oxide semiconductor layer, the source electrode and the drain electrode, and an upper gate electrode provided on the insulating layer. When viewed in a normal direction of the substrate, the upper gate electrode does not overlap a first electrode which is one of the source electrode and the drain electrode, and a second electrode which is the other of the source electrode and the drain electrode does not overlap the lower gate electrode.

A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage.

A method of constructing an integrated circuit (IC) includes fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer of the integrated circuit. The insulator layer is supported by a sacrificial substrate. The MOSFET includes an extended drain region. The method deposits a front-side dielectric layer on the MOSFET, bonds a handle substrate to the front-side dielectric layer, and then removes the sacrificial substrate. The method also fabricates multiple back gates on a second surface of the insulator layer. The second surface is opposite the first surface.

Methods of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high E.sub.crit semiconductors are presented. A dielectric layer is deposited on a high E.sub.crit substrate. The dielectric layer is etched to form a drift region. A refractory material is deposited on the substrate and dielectric layer. The refractory material is etched to form a gate length. Implant ionization is applied to form high-conductivity and high-critical field strength source with SAG and SAD features. The device is annealed to activate the contact regions. Alternately, a refractory material may be deposited on a high E.sub.crit substrate. The refractory material is etched to form a channel region. Implant ionization is applied to form high-conductivity and high E.sub.crit source and drain contact regions with SAG and SAD features. The refractory material is selectively removed to form the gate length and drift regions. The device is annealed to activate the contact regions.

A high voltage thin-film transistor is specified comprising a gate electrode (G11, G21) in a gate electrode layer (31), a semiconductive channel (C11,C12) in a channel layer (34) parallel to the gate electrode layer and being electrically insulated from the gate electrode by a gate dielectric layer (32). The transistor further comprises a dominant main electrode and a subordinate main electrode (M11, M12). The main electrodes each have an external portion (M11e, M12e) in a main electrode layer (36) and an internal portion (M11e, M12e) that protrudes through a further dielectric layer (35) between the main electrode layer and the channel layer to electrically contact the semiconductive channel in a dominant main electrode contact area (M11c) and a subordinate main electrode contact area (M12c) respectively. A first distance (D1) is defined between a side of the dominant main electrode contact area facing the subordinate main electrode contact area and a side of the external portion of the dominant main electrode facing the external portion of the subordinate main electrode. A second distance (D2) is defined between a side of the subordinate main electrode contact area facing the dominant main electrode contact area and a side of the external portion of the subordinate main electrode facing the external portion of the dominant main electrode, wherein the first distance is at least twice as large as the second distance.

The present application discloses an array substrate having a plurality of subpixel areas. The array substrate includes a base substrate; a plurality of first thin film transistors on the base substrate, each of which being in one of the plurality of subpixel areas; and a plurality of capacitor electrodes, each of which being in one of the plurality of subpixel areas. Each of the plurality of first thin film transistors includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes a first semi-conductive channel part, a first conductive part electrically connected to the first drain electrode, and a second conductive part electrically connected to the first source electrode. Each of the plurality of capacitor electrodes, the insulating layer, and the first conductive part constitute a first storage capacitor in one of the plurality of subpixel areas.

A semiconductor device includes: a first gate structure on a substrate; a first drain region having a first conductive type adjacent to one side of the first gate structure; a source region having the first conductive type adjacent to another side of the first gate structure; and a first body implant region having a second conductive type under part of the first gate structure.

Provided are a transistor array substrate and an electronic device. A first active layer includes a first area, a second area spaced apart from the first area, and a channel area provided between the first area and the second area. A gate insulating film is disposed on the first active layer. A gate electrode is disposed on the gate insulating film to overlap a portion of the channel area of the first active layer. The gate electrode overlaps a portion of at least one area of the first and second areas of the first active layer. Deteriorations in the channel area are prevented.