An integrated circuit device includes a first wiring, a second wiring, a semiconductor member that is connected between the first and second wirings, an electrode, and an insulating film that is provided between the semiconductor member and the electrode. The semiconductor member includes a first semiconductor portion of a first conductivity type connected to the first wiring, a second semiconductor portion of the first conductivity type, a third semiconductor portion of the first conductivity type, a fourth semiconductor portion of the first conductivity type, a fifth semiconductor portion of a second conductivity type, and a sixth semiconductor portion of the first conductivity type in this order. A first edge of the electrode on a side of the first wiring overlaps the second, third, or fourth semiconductor portions.

The embodiments of the present invention disclose a low temperature poly-silicon (LTPS) transistor array substrate and a method of fabricating the same, and a display device. The LTPS transistor array substrate comprises a substrate; a poly-silicon semiconductor active region provided on the substrate; a gate insulated from the poly-silicon semiconductor active region; and a dielectric spacer region provided on a side wall of the gate, wherein a portion of the poly-silicon semiconductor active region corresponding to the dielectric spacer region comprises a buffer region, and the dielectric spacer region surrounds the side wall of the gate and covers the buffer region.

Even when a light shielding film is provided between a transistor and a substrate, a threshold voltage of the transistor can be prevented or suppressed from being shifted. A display device includes light shielding films provided between a substrate and a semiconductor layer of a transistor including a gate electrode and the semiconductor layer. The semiconductor layer includes a source region and a drain region. Both of the light shielding films overlap the semiconductor layer when seen in a plan view, and are spaced apart from each other in a direction.

An object is to achieve high electrical characteristics (a high on-state current value, an excellent S value, and the like) and a highly reliable semiconductor device. A high on-state current value is achieved, whereby a further reduction in channel width (W) is achieved. A second conductive layer functioning as a gate electrode has a function of electrically surrounding side surfaces of a semiconductor film in a cross section in a channel width direction. With this structure, on-state current of a transistor can be increased. To achieve a semiconductor device with less hot-carrier degradation, the gate electrode has a tapered portion.

A semiconductor device (1001) includes a first thin film transistor (201) including a first semiconductor layer (3A), a gate insulating layer (5), a first gate electrode (7A) provided on the gate insulating layer (5), and first source and drain electrodes (8A), (9A), the first semiconductor layer (3A) including a first channel region (30A) and a first high-density impurity region (33sA), (33dA) containing an impurity of a first conductivity type. The first channel region (30A) includes a first channel portion (31A) and a second channel portion (32A) located between the first channel portion and the first high-density impurity region. The first channel portion (31A) contains an impurity of a second conductivity type that is different from the first conductivity type at a density higher than that in the second channel portion (32A) and the impurity of the first conductivity type at a density substantially equal to that in the second channel portion (32A).

A high voltage transistor may be formed on the basis of CMOS techniques for forming sophisticated SOI devices, wherein a fully depleted channel portion may result in low on-resistance and high breakdown voltage. Thus, an LDMOS-type transistor may be formed on the basis of a fully depleted drift region, thereby providing a high degree of scalability and process compatibility with sophisticated CMOS techniques.

The present invention provides a thin-film transistor and a manufacturing method thereof. The manufacturing method of the thin-film transistor according to the present invention is such that by forming a first photoresist layer on an active layer and using a mask associated with the active layer to pattern the first photoresist layer so as to form the first photoresist pattern, the first photoresist pattern so formed provides protection of the active layer against corrosion caused by acidic etchant solution in the subsequently conducted etching operation of source and drain electrodes so as to function as an etching stopper layer and further, a major portion of the first photoresist pattern can be removed in a photolithographic process of the source and drain electrodes so that only a minor portion is left in the finally-formed thin-film transistor and does not affect the properties of the thin-film transistor. The thin-film transistor according to the present invention has a simple manufacturing process and a low manufacturing cost and the surface of the active layer is flat and smooth. The thin-film transistor shows excellent properties.

A low temperature polysilicon (LTPS) thin film transistor (TFT) substrate and a method for manufacturing the same are provided. The method includes: sequentially forming a plurality of light-shielding portions, a buffer layer, and a plurality of island-shaped polysilicon portions on a substrate; performing light ion doping over two sides of the island-shaped polysilicon portions to form doped regions and channel regions; sequentially forming a gate insulating layer and a plurality of gate electrodes; performing heavy ion doping over the doped region that are not covered by the gate electrodes to form N-type heavily doped regions and N-type lightly doped regions; and forming an interlayer insulating layer as well as a source electrode and a drain electrode which are electrically connected to the N-type heavily doped regions on the gate electrodes.

A thin-film transistor (TFT) and a manufacturing method thereof, an array substrate and a display device are provided. The TFT includes: a base substrate; a gate electrode and a gate insulating layer, disposed on the base substrate; and an active layer, wherein the gate insulating layer is disposed between the active layer and the gate electrode; the active layer includes a channel region and a doped region disposed on at least one side of the channel region; and the gate insulating layer is provided with a protrusion which is disposed between the doped region and the gate electrode.

A thin film transistor includes a substrate, a semiconductor layer, a first insulating layer, and a gate electrode. The gate electrode overlaps the semiconductor layer. The thin film transistor includes a second insulating layer on the gate electrode, and an electrode structure on the second insulating layer. The electrode structure is connected to the gate electrode through a via hole. The thin film transistor includes a source electrode and a drain electrode passing through the first insulating layer and the second insulating layer to be connected to the semiconductor layer. The semiconductor layer includes a channel area overlapping the gate electrode, a source area connected to the source electrode, a drain area connected to the drain electrode, a lightly doped source area, and a lightly doped drain area. The electrode structure overlaps at least one of the lightly doped source area or the lightly doped drain area.