A display device may include a light emitting element, a buffer layer, a gate insulation layer, and a switching element. A refractive index of the gate insulation layer may be equal to a refractive index of the buffer layer. The switching element may be electrically connected to the light emitting element and may include an active layer and a gate electrode. The active layer may be positioned between the buffer layer and the gate insulation layer and may directly contact at least one of the buffer layer and the gate insulation layer. The gate insulation layer may be positioned between the active layer and the gate electrode and may directly contact at least one of the active layer and the gate electrode.

A display apparatus includes a first pad at one side of a substrate; a first semiconductor layer on the substrate; a first crack detection electrode interposed between the substrate and the first semiconductor layer, and including a first end portion at the one side and a second end portion at another side; a second crack detection electrode disposed on the first semiconductor layer, and including a first end portion located at the one side and a second end portion connected to the second end portion of the first crack detection electrode; and a first auxiliary electrode disposed on the second conductive layer, and including a first end portion connected to the second end portion of the first crack detection electrode and a second end portion electrically connected to the first pad.

The disclosure is related to a display panel having a touch function and manufacture thereof, and the composite electrode thereof. The display panel comprises a composite electrode. The composite electrode comprises a metal electrode and a metal oxide layer formed on the surface of the metal electrode. Through the above configuration, the dense and insulated metal oxide layer is formed on the surface of the metal electrode of the composite electrode to prevent the composite electrode from forming a short-circuit with the peripheral circuits. Thus the yield for the display panel with a touch function is increased and the cost is reduced.

A display device includes a switching transistor, a driving transistor, a storage capacitor connected to the switching and driving transistors, and an organic light-emitting diode connected to the driving transistor. The driving transistor is connected to the switching transistor. The driving transistor includes a semiconductor layer having a channel region, first doped regions at sides of the channel region, and second doped regions doped with impurities of a concentration greater than the first doped regions. A first electrode layer is over an insulating layer, which covers the semiconductor layer. The electrode layer includes convex portions extending toward the first doped regions and covering an end of the channel region. At least one of the convex portions has a width greater than or equal to a width of the end of the channel region.

A first semiconductor layer is formed on an insulating surface. A first insulating layer for covering an upper side of the first semiconductor layer is formed. On the first insulating layer, a second semiconductor layer is formed. A second insulating layer for covering an upper side of the second semiconductor layer is formed. A first contact hole extending through the first and second insulating layers to reach the first semiconductor, and a second contact hole extending through the second insulating layer to reach the second semiconductor layer but not reaching the first insulating layer are opened. After the step of forming the second insulating layer before the step of opening the first and second contact holes, laser or heat annealing process is executed.

A plurality of thin film transistors provided in a peripheral region are first staggered thin film transistors where a first channel layer configured of low-temperature polysilicon is included, and the first channel layer is not interposed between a first source electrode and a first gate electrode, and between a first drain electrode and the first gate electrode. A plurality of thin film transistors provided in a display region are second staggered thin film transistors where a second channel layer configured of an oxide semiconductor is included, and the second channel layer is not interposed between a second source electrode and a second gate electrode, and between a second drain electrode and the second gate electrode. The first thin film transistor is located below the second thin film transistor.

A thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are disclosed. The manufacturing method of the array substrate includes depositing an amorphous silicon thin film layer on a base substrate; performing a patterning process on the amorphous silicon thin film layer, so as to form a pattern with multiple small pores at a surface of the amorphous silicon thin film layer. With this method, when a laser annealing treatment of amorphous silicon is performed, the molten silicon after melting fills the space of small pores at a surface of the amorphous silicon thin film layer firstly, thereby avoiding forming a protruded grain boundary that is produced because the excess volume of polysilicon is squeezed.

A display device includes an array substrate defined with a plurality of pixel structures arranged in an array. Each of the pixel structures includes a semiconductor layer disposed over a substrate and a first metal layer disposed over the substrate. The pixel structure includes a first insulating layer disposed over the semiconductor layer, having a first opening exposing a top surface of the semiconductor layer and a sidewall surface of the first insulating layer. The pixel structure includes a metal pad disposed over the first insulating layer, being formed over the top surface of the semiconductor layer and the sidewall surface of the first insulating layer through the first opening. The pixel structure includes a second insulating layer disposed over the metal pad and the first insulating layer, having a second opening exposing the metal pad over the sidewall surface of the first insulating layer.

Techniques are provided for forming thin film transistors having a polycrystalline silicon active layer formed by metal-induced crystallization (MIC) of amorphous silicon in an oxidizing atmosphere. In an aspect, a transistor device, is provided that includes a source region and a drain region formed on a substrate, and an active channel region formed on the substrate and electrically connecting the source region and the drain region. The active channel region is formed with a polycrystalline silicon layer having resulted from annealing an amorphous silicon layer formed on the substrate and having a metal layer formed thereon, wherein the annealing of the amorphous silicon layer was at least partially performed in an oxidizing ambience, thereby resulting in crystallization of the amorphous silicon layer to form the polycrystalline silicon layer.

According to one embodiment, a thin film transistor includes an oxide semiconductor layer provided above an insulating substrate and including a channel region between a source region and a drain region, a first insulating film provided in a region on the oxide semiconductor layer, which corresponds to the channel region, a gate electrode provided on the first insulating film, a first protective film provided on the oxide semiconductor layer, the first insulating film and the gate electrode, as an insulating film containing a metal, a second protective film provided on the first protective film and a third protective film provided on the second protective film, as an insulating film containing a metal.