A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

An array substrate includes a substrate, a first thin film transistor, and a second thin film transistor, and the first thin film transistor and the second thin film transistor each are located on a same side of the substrate. The first thin film transistor includes a first active layer being a polysilicon layer, and the second thin film transistor includes a second active layer being an oxide semiconductor layer and includes a first contact layer and a second contact layer. The first contact layer is located between the substrate and the second active layer, the second contact layer is located on a side of the second active layer facing away from the substrate, the first contact layer and the second contact layer each are in contact with the second active layer, and the second active layer, the first contact layer, and the second contact layer each are island-shaped.

There is provided a display device including: a light emitting element; and a drive transistor (DRTr) that includes a coupling section (W1) and a plurality of channel sections (CH) coupled in series through the coupling section (W1), wherein the drive transistor (DRTr) is configured to supply a drive current to the light emitting element.

The invention discloses a thin film transistor, a display panel and a method of fabricating the thin film transistor. The thin film transistor includes a substrate, a flat film, a dielectric layer, an active layer, and a source/drain layer which are stacked in sequence from bottom to top; and a plurality of reinforcing portions are disposed on an upper surface of the flat film, wherein the flat film and the reinforcing portions constitute a gate layer, wherein the reinforcing portions are configured to increase an area of the upper surface of the flat film, so as to increase an effective overlapping area between the flat film and the active layer, and reduce a width and a length of the thin film transistor.

A thin film transistor includes an active layer, a source electrode and a drain electrode. The active layer includes a conductive region and the conductive region is between the source electrode and the drain electrode and is spaced apart from at least one of the source electrode and the drain electrode.

A display panel is provided. A first metal layer is patterned to form a first electrode and a second metal layer is patterned to form a second electrode. A projection of the second electrode and a projection of the first electrode are overlapped on a substrate. A gate insulating layer is disposed between the first metal layer and the second metal layer. A test circuit layer is electrically connected to the second electrode. An electrostatic test electrode includes a first test electrode and a second test electrode. The first test electrode is electrically connected to the first electrode and the second test electrode is electrically connected to the test circuit layer. The gate insulating layer disposed in an intermediate region has an antistatic ability.

According to one embodiment, a display device includes a display panel and a drive circuit. A transistor provided in a pixel portion or a peripheral portion of the display panel includes a semiconductor layer having a first end and a second end, first and second gate electrodes overlapping the semiconductor layer, a source electrode connected to the first end, and a drain electrode connected to the second end. The first and second gate electrodes are disposed in a first layer. The source electrode and the drain electrode are disposed in a second layer. The source electrode is formed to cover at least a first channel region in planar view. The drain electrode is formed to cover at least a second channel region in planar view.

The present application discloses a thin film transistor having an active layer including a channel part, a source contact part, and a drain contact part. At least one of the source contact part and the drain contact part has a contacting edge having one or more irregularities along the contacting edge.

In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.

A liquid crystal display includes: a gate line connected to a gate electrode; a semiconductor layer disposed on the gate line and including silicon; an ohmic contact layer disposed on the semiconductor layer; and a data conductor disposed on the ohmic contact layer. The semiconductor layer includes a source region, a drain region, and a channel region disposed between the source region and the drain region. The data conductor includes a data line transmitting a data signal, a source electrode corresponding to the source region, and a drain electrode corresponding to the drain region. A channel step of the semiconductor layer is a height difference between an upper surface in the source region or the drain region and an upper surface in the channel region. The upper surface in the source region or the drain region has a maximum height of the semiconductor layer.