Improved electrical and thermal properties of solder alloys are achieved by the use of micro-additives in solder alloys to engineer the electrical and thermal properties of the solder alloys and the properties of the reaction layers between the solder and the metal surfaces. The electrical and thermal conductivity of alloys and that of the reaction layers between the solder and the -metal surfaces can be controlled over a wide range of temperatures. The solder alloys produce stable microstructures wherein such stable microstructures of these alloys do not exhibit significant changes when exposed to changes in temperature, compared to traditional interconnect materials.

A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

Various embodiments include a solder preform for establishing a diffusion solder connection comprising: a microstructure including a solder material and a metallic material; a first joining surface for a first joining partner and a second joining surface for a second joining partner; and a diffusion zone comprising an intermetallic compound of at least some of the solder material and at least some of the metallic material. The first joining surface and the second joining surface include at least some solder material.

Various embodiments include a solder preform for establishing a diffusion solder connection comprising: a microstructure including a solder material and a metallic material; a first joining surface for a first joining partner and a second joining surface for a second joining partner; and a diffusion zone comprising an intermetallic compound of at least some of the solder material and at least some of the metallic material. The first joining surface and the second joining surface include at least some solder material.

A method of soldering elements together includes providing a substrate having a metal die attach surface, providing a semiconductor die that is configured as a power semiconductor device and having a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack having a front side metallization and a contaminant protection layer, arranging the semiconductor die on the substrate with a region of solder material between the die attach surface and the rear side metallization, and performing a soldering process that reflows the region of solder material to form a soldered joint between the metal die attach surface and the rear side metallization, wherein the soldering process comprises applying mechanical pressure to the front side metallization, and wherein the contaminant protection layer is configured to prevent transmission of contaminants into the semiconductor body after the soldering process is completed.

A semiconductor device includes a first die pad, a second die pad, a first semiconductor element, a second semiconductor element, an insulating element, first terminals, second terminals, and a sealing resin. The sealing resin has a first side surface located on one side of a first direction, a second side surface located on the other side of the first direction, and third and fourth side surfaces that are separated from each other in a second direction orthogonal to both a thickness direction and the first direction and are connected to the first and second side surfaces. A first gate mark having a surface roughness larger than the other regions of the third side surface is formed on the third side surface. When viewed along the second direction, the first gate mark overlaps a pad gap provided between the first die pad and the second die pad in the first direction.

A semiconductor device includes a first die pad, a second die pad, a first semiconductor element, a second semiconductor element, an insulating element, first terminals, second terminals, and a sealing resin. The sealing resin has a first side surface located on one side of a first direction, a second side surface located on the other side of the first direction, and third and fourth side surfaces that are separated from each other in a second direction orthogonal to both a thickness direction and the first direction and are connected to the first and second side surfaces. A first gate mark having a surface roughness larger than the other regions of the third side surface is formed on the third side surface. When viewed along the second direction, the first gate mark overlaps a pad gap provided between the first die pad and the second die pad in the first direction.

Provided is a method of manufacturing a semiconductor having a double-sided substrate including preparing a first substrate on which a specific pattern is formed to enable electrical connection, preparing at least one semiconductor chip bonded to a metal post, bonding the at least one semiconductor chip to the first substrate, bonding a second substrate to the metal post, forming a package housing by packaging the first substrate and the second substrate to expose a lead frame, and forming terminal leads toward the outside of the package housing. Accordingly, the semiconductor chip and the metal post are previously joined to each other and are respectively bonded to the first substrate and the second substrate so that damage generated while bonding the semiconductor chip may be minimized and electrical properties and reliability of the semiconductor chip may be improved.

A lead-free solder has a heat resistance temperature which is high and a thermal conductive property which is not changed in a high temperature range. A semiconductor device includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, and the remainder consisting of Sn and inevitable impurities. A bonding layer including the solder material, is formed between a semiconductor element and a substrate electrode or a lead frame.

A semiconductor device according to the embodiment may include a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer; a first bonding pad disposed on the light emitting structure and electrically connected to the first conductivity type semiconductor layer; a second bonding pad disposed on the light emitting structure and spaced apart from the first bonding pad, and electrically connected to the second conductivity type semiconductor layer; and a reflective layer disposed on the light emitting structure and disposed between the first bonding pad and the second bonding pad. According to the semiconductor device of the embodiment, each of the first bonding pad and the second bonding pad includes a porous metal layer having a plurality of pores and a bonding alloy layer disposed on the porous metal layer.