A semiconductor device includes a first die pad, a second die pad, a first semiconductor element, a second semiconductor element, an insulating element, first terminals, second terminals, and a sealing resin. The sealing resin has a first side surface located on one side of a first direction, a second side surface located on the other side of the first direction, and third and fourth side surfaces that are separated from each other in a second direction orthogonal to both a thickness direction and the first direction and are connected to the first and second side surfaces. A first gate mark having a surface roughness larger than the other regions of the third side surface is formed on the third side surface. When viewed along the second direction, the first gate mark overlaps a pad gap provided between the first die pad and the second die pad in the first direction.

A semiconductor device includes a first die pad, a second die pad, a first semiconductor element, a second semiconductor element, an insulating element, first terminals, second terminals, and a sealing resin. The sealing resin has a first side surface located on one side of a first direction, a second side surface located on the other side of the first direction, and third and fourth side surfaces that are separated from each other in a second direction orthogonal to both a thickness direction and the first direction and are connected to the first and second side surfaces. A first gate mark having a surface roughness larger than the other regions of the third side surface is formed on the third side surface. When viewed along the second direction, the first gate mark overlaps a pad gap provided between the first die pad and the second die pad in the first direction.

A semiconductor die attach composition with greater than 60% metal volume after thermal reaction having: (a) 80-99 wt % of a mixture of metal particles comprising 30-70 wt % of a lead-free low melting point (LMP) particle composition comprising at least one LMP metal Y that melts below a temperature T1, and 25-70 wt % of a high melting point (HMP) particle composition comprising at least one metallic element M that is reactive with the at least one LMP metal Y at a process temperature T1, wherein the ratio of wt % of M to wt % of Y is at least 1.0; (b) 0-30 wt % of a metal powder additive A; and (c) a fluxing vehicle having a volatile portion, and not more than 50 wt % of a non-volatile portion.

The disclosed component module includes a component comprising at least one electric contact to which at least one porous contact piece is connected; the component module further includes a cooling system for fluid-based cooling, said cooling system comprising one or more cooling ducts which are formed by pores of the porous contact piece. The disclosed power module comprises a component module of said type.

A semiconductor assembly includes a substrate including a metal die attach surface, a semiconductor die that is arranged on the substrate, the semiconductor die being configured as a power semiconductor device and comprising a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack comprising a front side metallization and a contaminant protection layer that is between the front side metallization and the semiconductor body, and a diffusion soldered joint between the metal die attach surface and the rear side metallization, the diffusion soldered joint comprising one or more intermetallic phases throughout the diffusion soldered joint, wherein the contaminant protection layer is configured to prevent transmission of contaminants into the semiconductor body.

A method for high temperature bonding of substrates may include providing a top substrate and a bottom substrate, and positioning an insert between the substrates to form a assembly. The insert may be shaped to hold at least an amount of Sn having a low melting temperature and a gap shaped to hold at least a plurality of metal particles having a high melting temperature greater than the low melting temperature. The assembly may be heated to below the low melting temperature and held for a first period of time. The assembly may further be heated to approximately the low melting temperature and held for a period of time at a temperature equal to or greater than the low melting temperature such that the amount of Sn and the amount of metal particles form one or more intermetallic bonds. The assembly may be cooled to create a bonded assembly.

Bonded surfaces are formed by adhering first nanorods and second nanorods to respective first and second surfaces. The first shell is formed on the first nanorods and the second shell is formed on the second nanorods, wherein at least one of the first nanorods and second nanorods, and the first shell and the second shell are formed of distinct metals. The surfaces are then exposed to at least one condition that causes the distinct metals to form an alloy, such as eutectic alloy having a melting point below the temperature at which the alloy is formed, thereby bonding the surfaces upon which solidification of the alloy.

A mount structure includes two members that are bonded to each other with a bonding material layer having a first interface layer and a second interface layer at the interfaces with the two members. The bonding material layer contains a first intermetallic compound and a stress relaxation material. The first intermetallic compound has a spherical, a columnar, or an oval spherical shape, and the same crystalline structure as the first interface layer and the second interface layer, and partly closes the space between the first interface layer and the second interface layer. The stress relaxation material contains tin as a main component, and fills around the first intermetallic compound.

Improved electrical and thermal properties of solder alloys are achieved by the use of micro-additives in solder alloys to engineer the electrical and thermal properties of the solder alloys and the properties of the reaction layers between the solder and the metal surfaces. The electrical and thermal conductivity of alloys and that of the reaction layers between the solder and the -metal surfaces can be controlled over a wide range of temperatures. The solder alloys produce stable microstructures wherein such stable microstructures of these alloys do not exhibit significant changes when exposed to changes in temperature, compared to traditional interconnect materials.

To provide a lead-free solder the heat resistance temperature of which is high and thermal conductive property of which are not changed in a high temperature range. A semiconductor device of the present invention includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, and the remainder consisting of Sn and inevitable impurities, and a bonding layer including the solder material, which is formed between a semiconductor element and a substrate electrode or a lead frame.