There is provided a photoelectric conversion element which can prevent the contact resistance between a non-crystalline semiconductor layer containing impurities and an electrode formed on the non-crystalline semiconductor layer from increasing, and can improve the element characteristics. A photoelectric conversion element (10) includes a semiconductor substrate (12), a first semiconductor layer (20n), a second semiconductor layer (20p), a first electrode (22n), and a second electrode (22p). The first semiconductor layer (20n) has a first conductive type. The second semiconductor layer (20p) has a second conductive type opposite to the first conductive type. The first electrode (22n) is formed on the first semiconductor layer (20n). The second electrode (22p) is formed on the second semiconductor layer (20p). At least one electrode of the first electrode (22n) and the second electrode (22p) includes a plurality of metal crystal grains. The average crystal grain size of the metal crystal grains in the in-surface direction of electrode is greater than the thickness of the electrode.

The n-type amorphous semiconductor layers 4 are on parts of that one of the faces of the semiconductor substrate 1, there being provided no p-type amorphous semiconductor layers 5 in the parts. The electrodes 6 are disposed on the n-type amorphous semiconductor layers 4. The electrodes 7 are disposed on the p-type amorphous semiconductor layers 5. The p-type amorphous semiconductor layers 5 between those n-type amorphous semiconductor layers 4 which are adjacent along an in-plane direction of the semiconductor substrate 1 include, arranged along a first direction that points from the n-type amorphous semiconductor layers 4 toward the adjacent n-type amorphous semiconductor layers 4: first and second electrode-provided regions where the electrodes 7 are disposed; and a no-electrode-provided region, between the first and second electrode-provided regions, where there are provided no electrodes 7.

Lateral and vertical microstructure enhanced photodetectors and avalanche photodetectors are monolithically integrated with CMOS/BiCMOS ASICs and can also be integrated with laser devices using fluidic assembly techniques. Photodetectors can be configured in a vertical PIN arrangement or lateral metal-semiconductor-metal arrangement where electrodes are in an inter-digitated pattern. Microstructures, such as holes and protrusions, can improve quantum efficiency in silicon, germanium and III-V materials and can also reduce avalanche voltages for avalanche photodiodes. Applications include optical communications within and between datacenters, telecommunications, LIDAR, and free space data communication.

A solar processing unit (SPU) for the conversion of solar energy to electric power includes a heterostructure of sheets of two (2)-dimensional materials. The heterostructure is utilized to produce a crystalline structure, wherein elemental Boron (B) and elemental Nitrogen (N), contained in sheets of hexagonal Boron Nitride (hBN), are located as bookends to one or more Carbons (C)s, between at least one sheet of Graphene. Each absorbed photon produces Multi-Excitation Generation, wherein more than one electron is generated. The SPU produces a spin motion of the Boron atoms in one direction and the Nitrogen atoms in the opposite direction within hBN by placing an external fixed magnetic field perpendicular to the sheet of hBN and a second orthogonal magnetic field paired to the strength of the fixed magnetic field and tuned to the resonant magnetic frequency of Nitrogen-15 followed by Boron-11, thereby achieving the spin required for enhanced photonic absorption.

A visibly transparent planar structure using a CPA scheme to boost the absorption of a multi-layer thin-film configuration, requiring no surface patterning, to overcome the intrinsic absorption limitation of the absorbing material. This is achieved in a multi-layer absorbing Fabry-Perot (FP) cavity, namely a thin-film amorphous silicon solar cell. Omni-resonance is achieved across a bandwidth of 80 nm in the near-infrared (NIR), thus increasing the effective absorption of the material, without modifying the material itself, enhancing it beyond its intrinsic absorption over a considerable spectral range. The apparatus achieved an increased external quantum efficiency (EQE) of 90% of the photocurrent generated in the 80 nm NIR region from 660 to 740 nm as compared to a bare solar cell. over the spectral range of interest.

A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P— and N—Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering.

A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack.

A solar cell with a heterojunction is produced. A first amorphous nano- and/or microcrystalline semiconductor layer is formed on the front face of a crystalline semiconductor substrate to form front face emitter or a front face surface field layer. A second such layer is formed on the rear face of the substrate to form a rear face surface field layer or a rear face emitter. Electrically conductive, transparent front face and rear face electrode layers and a frontal metallic contact layer grid structure are formed. Surface selective frontal PECVD deposition forms an electrically non-conductive, transparent dielectric front face cover layer and with such a thickness to form a closed layer directly on deposition, without additional heat and/or chemical treatment, only on the areas surrounding the frontal contact layer grid structure but not on the frontal contact layer grid structure. Finally, a rear face metallization is formed.

An assembly for optical to electrical power conversion including a photodiode assembly having a substrate layer and an internal side, an antireflective layer, a heterojunction buffer layer adjacent the internal side; an active area positioned adjacent the heterojunction buffer layer, a plurality of n+ electrode regions and p+ electrode regions positioned adjacent the active area, and back-contacts configured to align with the n+ and p+ electrode regions. The active area converts photons from incoming light into liberated electron hole pairs. The heterojunction buffer layer prevents electrons and holes of the liberated electron hole pairs from moving toward the substrate layer. The plurality of electrode regions are configured in an alternating pattern with gaps between each n+ and p+ electrode region. The electrode regions receive and generate electrical current from migration of the electrons and the holes, provide electrical pathways for the electrical current, and provide thermal pathways to dissipate heat.