A frame 100 containing aperture(s) 102, 103, 104 is positioned on and joined to a permanent substrate 206a or temporary substrate 206b. Electrical component(s) 202, 203, 204 are placed into respective aperture(s) 102, 103, 104 with the leads 504, 1002 of the component(s) 202, 203, 204 positioned on and attached to the permanent substrate 206a or the temporary substrate 206b. Then an encapsulant 402, electrically insulating, but preferably thermally conductive, envelops the component(s) 102, 103, 104. At this point, temporary substrate 206b may be removed exposing component leads 1002. Or, if component(s) 102, 103, 104 are mounted on permanent substrate 206a, vias 502 extend from the surface of substrate 206a to leads 504. With leads 504, 1002 exposed, the completed subassembly 500, 1000 may be incorporated into various forms of reverse-interconnection process (RIP) assemblies as detailed in related applications.

A dual-display device includes a flexible substrate comprising first and second surfaces opposing each other, the first surface comprising a first area and a second area, the flexible substrate being bent to allow the first and second areas of the first surface to face each other, the second surface comprising first and second areas opposing the first and second areas of the first surface, respectively. The device further includes a first display unit formed over the first area of the second surface of the bent flexible substrate, and realizing an image; a second display unit formed over second area that is opposite to the first area of the second surface of the bent flexible substrate, electrically connected to the first display unit via lines, and realizing another image; and a common driver unit electrically connected to a pad area that extends from the first display unit, and configured to transmit at least a signal to drive the first display unit and the second display unit.

A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.

A frame 100 containing aperture(s) 102, 103, 104 is positioned on and joined to a permanent substrate 206a or temporary substrate 206b. Electrical component(s) 202, 203, 204 are placed into respective aperture(s) 102, 103, 104 with the leads 504, 1002 of the component(s) 202, 203, 204 positioned on and attached to the permanent substrate 206a or the temporary substrate 206b. Then an encapsulant 402, electrically insulating, but preferably thermally conductive, envelops the component(s) 102, 103, 104. At this point, temporary substrate 206b may be removed exposing component leads 1002. Or, if component(s) 102, 103, 104 are mounted on permanent substrate 206a, vias 502 extend from the surface of substrate 206a to leads 504. With leads 504, 1002 exposed, the completed subassembly 500, 1000 may be incorporated into various forms of reverse-interconnection process (RIP) assemblies as detailed in related applications.

Systems, processes, and manufactures are provided that employ a casing associated with an electrical component to provide some, most, substantially all or all electrical insulative protection necessary for the electrical component. This casing may be further employed with potting or other materials to supplement and add additional or different protections for the component. These additional protections can include additional insulative resistance, thermal protection, moisture protection and other buffers to and from the environment.

Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Production method for an electronic module, comprising a housing and at least one electronic assembly, wherein the electronic assembly is arranged, in particular at least partially, in an interior chamber of the housing, wherein, however, electrical contacts are guided through the housing wall, out of the interior chamber of the housing, to an outer face of the housing, wherein the interior chamber of the housing is filled with a casting compound at least in such a way that the casting compound covers passage points in the housing wall at which the electrical contacts are guided through the housing wall, wherein a layer of the at least one assembly is removed at least in the region of the passage points in the housing wall.

A flexible printed circuit assembly, having a first flexible printed circuit having a first conductive layer and a device that is connected the first conductive layer; and a second flexible printed circuit having a second conductive layer, an insulating center layer, and a third conductive layer, the insulating center layer arranged in-between the second and the third conductive layers, the second conductive layer and the insulating center layer being removed to form an opening to expose an upper surface of the third conductive layer, wherein the first flexible printed circuit is arranged such that the device is accommodated inside the opening, a lower surface of the device being in thermal connection with the third conductive layer, and the first conductive layer is arranged to be in electrical connection with the second conductive layer.

The present invention provides a piezoelectric quartz crystal resonator and a method for fabricating the same. The piezoelectric quartz crystal resonator comprises a circuit board, a quartz crystal resonator, and a thermistor; wherein, the thermistor is configured to detect a temperature of the quartz crystal resonator, the thermistor and the quartz crystal resonator are arranged on the circuit board and interconnected with each other via electric wires arranged on the circuit board; the thermistor and the quartz crystal resonator are sealed independently from each other by thermoplastic material, and the thermoplastic material sealing the thermistor is in contact with the thermoplastic material sealing the quartz crystal resonator.

The present disclosure discloses a method for providing protective coatings onto an energizable LED component coupled to an electrical path. More particularly, the present disclosure relates to LED lamps comprising transparent dielectric coatings and LED lamps and devices made thereby.