A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provided and an electrically conductive contact extends within the insulating multilayer to emerging onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.

Performances of a semiconductor device are improved. The semiconductor device has: a gate electrode formed on an SOI layer of an SOI substrate via a gate insulating film having a charge storage film therein; an n-type semiconductor region and a p-type semiconductor region respectively formed on SOI layers on both sides of the gate electrode. A memory cell MC serving as a non-volatile memory cell is formed of the gate insulating film, the gate electrode, the n-type semiconductor region and the p-type semiconductor region.

An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a coupling transistor made of a p-channel MOSFET and formed in an n.sup.-type semiconductor region over a base made of a p-type semiconductor. The coupling transistor has a resurf layer as a p-type semiconductor region and couples a lower-voltage circuit region to a higher-voltage circuit region to which a power supply potential higher than the power supply potential supplied to the lower-voltage circuit region is supplied. The semiconductor device has a p-type semiconductor region formed in the portion of the n.sup.-type semiconductor region which surrounds the coupling transistor in plan view.

A method of manufacturing a semiconductor device with a fuse is provided including the steps of providing a semiconductor-on-insulator (SOI) structure including an insulating layer and a semiconductor layer formed on the insulating layer, forming a first raised semiconductor region on the semiconductor layer and a second raised semiconductor region on the semiconductor layer adjacent to the first semiconductor region, and performing a silicidation process of the first and second raised semiconductor regions to form a first at least partially silicided raised semiconductor region with a first silicided portion and a second at least partially silicided raised semiconductor region with a second silicided portion.

A semiconductor device is provided. The semiconductor device includes a template layer disposed over a substrate and having a trench therein, a buffer structure disposed over a bottom surface of the trench and comprising a metal oxide, a single crystal semiconductor structure disposed within the trench and over the buffer structure and a gate structure disposed over a channel region of the single crystal semiconductor structure.

A semiconductor device is provided. The semiconductor device includes a metal layer, a semiconductor layer in electrical contact with the metal layer, a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure, and a metal compound layer disposed between the 2D material layer and the semiconductor layer.

A method of preparing a semiconductor structure includes forming an insulating layer having a thickness between about 5 nm and about 100 nm on a substrate, and forming an active layer comprising a tensile-strained silicon over the insulating layer. At least a portion of the active layer is implanted with ions to render at least a portion of the active layer amorphous and reduce the tensile strain in the at least portion of the active layer. The method further includes thermally annealing the implanted portion of the active layer and recrystallizing such previously rendered amorphous portion of the active layer. A germanium condensation process is performed on the recrystallized portion of the active layer to form a SiGe material having a compressive strain. Also described are the semiconductor structures.

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises one or more semiconductor layers, a gate on the one or more semiconductor layers, a source/drain region including a first portion in the one or more semiconductor layers and a second portion in the one or more semiconductor layers, and a defect region in the one or more semiconductor layers. The defect region is disposed adjacent to the first portion of the source/drain region.

Various methods and devices that involve self-aligned features on a semiconductor on insulator process are provided. An exemplary method comprises forming a gate on a semiconductor on insulator wafer. The semiconductor on insulator wafer comprises a device region, a buried insulator, and a substrate. The exemplary method further comprises applying a treatment to the semiconductor on insulator wafer using the gate as a mask. The treatment creates a treated insulator region in the buried insulator. The exemplary method also comprises removing at least a portion of the substrate. The exemplary method also comprises, selectively removing the treated insulator region from the buried insulator to form a remaining insulator region after removing that portion of the substrate.