A fully depleted field effect transistor (FET) and an anti-fuse structure are provided on a same chip. The fully depleted FET and the anti-fuse structure share a same high dielectric (k) constant dielectric material. The anti-fuse structure contains a faceted epitaxial doped semiconductor material as a bottom electrode, a high k dielectric material portion, and a gate electrode material portion as a top electrode. The sharp corners of the faceted epitaxial doped semiconductor material cause electric field concentration, which aid in the reduction of the breakdown voltage of the anti-fuse structure.

The invention provides the guided design approach to optimize the device performance for a best area-efficient layout footprint in a single-leg MOS device that is based on any of the SOI, SOS or SON technologies. The design methodology depends on a new proprietary device architecture that is also being claimed in this patent and that allows the implementations of the design equations of our methodology.

The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.

The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.

In one example implementation, the present disclosure provides a modular approach to reducing flicker noise in metal-oxide semiconductor field-effect transistors (MOSFETs) in a device. First, a circuit designer may select one or more surface channel MOSFETs in a device. Then, the one or more surface channel MOSFETs are converted to one or more buried channel MOSFETs to reduce flicker noise. One or more masks may be applied to the channel(s) of the one or more surface channel MOSFETs. The technique maybe used at the input(s) of operational amplifiers, and more particularly, rail-to-rail operational amplifiers, as well as other analog and digital circuits such a mixers, ring oscillators, current mirrors, etc.

Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.

A semiconductor device includes an insulating layer, a first semiconductor layer over the insulating layer, a diffusion break structure between a first active region and a second active region and including a first insulating pattern over the insulating layer and an opening over the first insulating pattern, and a conductive gate material over the opening.

The invention provides a semiconductor structure comprising a silicon-on-insulator (SOI) substrate, which comprises a silicon layer and an insulating layer stacked from bottom to top, a phosphosilicate glass (PGS) on the insulating layer, and a fluorosilicate glass (FSG) on the phosphosilicate glass. The probability of ions infiltrating into the transistor can be reduced and the yield of products can be improved.

A radio frequency (RF) switch includes a semiconductor-on-insulator (SOI) substrate including a handle wafer, a buried oxide over the handle wafer, and a thin semiconductor layer over the buried oxide. A transistor is situated in the thin semiconductor layer and includes a gate, a source, a drain. The buried oxide can have a thickness of approximately two thousand angstroms (2,000 ) to approximately six thousand angstroms (6,000 ). The thin semiconductor layer has a thickness less than approximately four hundred angstroms (400 ), so as to increase maximum power handling (P.sub.MAX) of the transistor. Nickel silicides can be situated on the source and the drain in an upper portion of the thin semiconductor layer. The RF switch can be one of a plurality of RF switches situated between an RF input and an RF output of an RF device.

A field effect transistor includes a source region of a first conductive type on a device layer, a drain region of the first conductive type, a body region of a second conductive type that is opposite to the first conductive type, and a gate electrode on the device layer. The body region is directly below the gate electrode. When the insulating surface is in plan view, the gate electrode and the body region each have a shape elongated in a first direction, the source region is on one side of the gate electrode, and the drain region is on another side of the gate electrode. The field effect transistor further includes a body-contact region of the second conductive type extending from each of a plurality of body-contact connecting portions on an edge of the body region facing the source region toward the source region.