An array substrate comprises a substrate, a common electrode formed on the substrate, a light shielding layer disposed on the common electrode, an insulating layer disposed on the light shielding layer and the common electrode, a poly-silicon layer, a gate insulating layer, a gate connected with the common electrode by a hole, a medium layer and a source drain. A method for manufacturing the array substrate comprises forming a transparent conductive layer and a first metallic layer on the substrate, forming patterned common electrode and light shielding layer by multiple steps of etching so that a process of photomask can be saved, and forming holes connecting with the common electrode and the gate by a photomask etching process, then manufacturing a medium layer and a source drain. The method adopts seven processes of photomask so that the process is simplified, and the cost is lowered.

A structure with which the zero current of a field effect transistor using a conductor-semiconductor junction can be reduced is provided. A floating electrode (102) including a conductor or a semiconductor and being enclosed by an insulator (104) is formed between a semiconductor layer (101) and a gate (105) so as to cross the semiconductor layer (101) and the floating electrode (102) is charged, whereby carriers are prevented from flowing from a source electrode (103a) or a drain electrode (103b). Accordingly, a sufficiently low carrier concentration can be kept in the semiconductor layer (101) and thus the zero current can be reduced.

A display panel including a first substrate, a second substrate and a display medium is provided. The first substrate includes a base substrate, a gate, an active layer, a source, a drain, and a shielding structure. The gate is disposed on the base substrate. The active layer is electrically insulated from and disposed correspondingly to the gate. The source and the drain are electrically connected to the active layer. The shielding structure is disposed on the active layer and covers at least part of the active layer. The shielding structure includes a metal layer and an anti-reflection structure. The display medium is disposed between the first substrate and the second substrate.

A liquid crystal display device includes a gate line in a first direction, a data line in a second direction intersecting the first direction, a pixel including a first region having a transistor connected to the gate and data lines, and a contact hole connecting the transistor to a pixel electrode, and a second region having the pixel electrode, wherein a length of a first width along the first direction on the first region is longer than a length of a second width along the second direction on the first region, and wherein a length of a third width along the first direction on the second region is longer than a length of a fourth width along the second direction on the second region.

A manufacturing method of an array substrate, an array substrate and a display device are provided. The method includes the following operations: forming a light shielding layer formed of a metal blacken production on a base substrate, wherein the metal blacken production is a product by blackening a metal; forming a preset film layer on the base substrate which is provided with the light shielding layer; forming both a pattern of the light shielding layer and a pattern of the preset film layer through one patterning process. The method of forming a pattern of the light shielding layer and a pattern of the preset film layer through one patterning process saves one patterning process.

A display device is provided. The display device can include a first pixel portion comprising a first thin-film transistor provided at the intersection between a first gate line and a first data line, and a first pixel electrode connected to the first thin-film transistor, and a second pixel portion comprising a second thin-film transistor provided at the intersection between a second gate line and the first data line, and a second pixel electrode connected to the second thin-film transistor, wherein the first pixel portion and the second pixel portion are arranged parallel to the first data line, and directions extended the first pixel electrode and the second pixel electrode are extended in such a direction as to face each other.

A free-form display is disclosed which makes a step-like pattern adjacent to a free-form portion less visible. The free-form display has an active area and a bezel area, and at least part of a boundary between the active area and the bezel area has a free-form portion. The free-form portion comprises subpixel electrodes and a light blocking portion. A plurality of subpixel electrodes are placed in areas defined by a plurality of gate lines and a plurality of data lines that intersect each other. A light blocking portion has openings exposing the subpixel electrodes, respectively, and is arranged to overlap the gate lines and the data lines. The active area comprises subpixel areas where the subpixel electrodes are placed, and a non-pixel area where no subpixel electrodes are placed. The openings of the light blocking portion adjacent to the non-pixel area, are made in different sizes.

The present invention provides a method for manufacturing the N-type TFT, which includes subjecting a light shielding layer to a grating like patternization treatment for controlling different zones of a poly-silicon layer to induce difference of crystallization so as to have different zones of the poly-silicon layer forming crystalline grains having different sizes, whereby through just one operation of ion doping, different zones of the poly-silicon layer have differences in electrical resistivity due to difference of grain size generated under the condition of identical doping concentration to provide an effect equivalent to an LDD structure for providing the TFT with a relatively low leakage current and improved reliability. Further, since only one operation of ion injection is involved, the manufacturing time and manufacturing cost can be saved, damages of the poly-silicon layer can be reduced, the activation time can be shortened, thereby facilitating the manufacture of flexible display devices.

A display device may include a substrate and a first roof layer portion that is formed of a roof layer material and overlaps the substrate in a direction, the direction is perpendicular to a surface of the substrate. A lateral surface of the first roof layer portion is disposed in a plane. The display device may further a second roof layer portion formed of the roof layer material and separated from the first roof layer portion. The display device may further a common electrode portion disposed between the first roof layer portion and the substrate in the direction. A lateral surface of the common electrode portion is disposed in the plane or is spaced from the lateral surface of the first roof layer portion in a second direction parallel to the surface of the substrate. The display device may further a pixel electrode disposed between the first common electrode portion and the substrate.

An integration method of fabricating optical sensor device and thin film transistor device includes the follow steps. A substrate is provided, and a gate electrode and a bottom electrode are formed on the substrate. A first insulating layer is formed on the gate electrode and the bottom electrode, and the first insulating layer at least partially exposes the bottom electrode. An optical sensing pattern is formed on the bottom electrode. A patterned transparent semiconductor layer is formed on the first insulating layer, wherein the patterned transparent semiconductor layer includes a first transparent semiconductor pattern covering the gate electrode, and a second transparent semiconductor pattern covering the optical sensing pattern. A source electrode and a drain electrode are formed on the first transparent semiconductor pattern. A modification process including introducing at least one gas is performed on the second transparent semiconductor pattern to transfer the second transparent semiconductor pattern into a conductive transparent top electrode.