An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

A display device including: a lead wiring layer pattern 207, made from metal, that extends outside a region 10A on a substrate in which a light-emitter is present; a passivation layer 216; a contact hole 216a in the passivation layer 216 outside the region 10A in a position over the lead wiring layer pattern 207 in plan view; a connecting wiring layer pattern 237 that is continuous across the passivation layer 216, an inner circumference of the contact hole 216a, and the lead wiring layer pattern 207 in the contact hole 216a; a sealing layer 217 covering a portion of the connecting wiring layer pattern 237 in the contact hole 216a; and an upper sealing layer pattern 219 covering the sealing layer pattern 217 that is above the connecting wiring layer pattern 237.

A thin film transistor is provided, which includes a gate electrode on a substrate; a channel layer overlapping the gate electrode; a dielectric layer between the gate electrode and the channel layer; a source electrode and a drain electrode electrically connecting to the channel layer; a passivation layer overlying the source electrode, the drain electrode, and the gate dielectric layer, wherein the channel layer includes two contact portions being in contact with the source electrode and the drain electrode, respectively, and a non-contact portion located between the two contact portions, and wherein one of the two contact portions has a first thickness in a first direction perpendicular to a surface of the substrate, and the non-contact portion has a second thickness less than the first thickness in the first direction.

By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.

A highly reliable semiconductor device which uses an oxide semiconductor film for a backplane is provided. A semiconductor device includes a first conductive film, a first insulating film over the first conductive film, an oxide semiconductor film which is over the first insulating film and overlaps with the first conductive film, a second insulating film over the oxide semiconductor film, and a pair of second conductive films electrically connected to the oxide semiconductor film through an opening portion included in the second insulating film. The second insulating film overlaps with a region of the oxide insulating film in which a carrier flows between the pair of second conductive films and overlaps with end portions of the oxide semiconductor film.

The present invention provides a dual gate TFT substrate structure utilizing COA skill, comprising a substrate (1), a bottom gate (2) positioned on the substrate (1), a bottom gate isolation layer (3) covering the bottom gate (2) and the substrate (1), an active layer (4) positioned on the bottom gate isolation layer (3) above the bottom gate (2), an etching stopper layer (5) positioned on the active layer (4) and the bottom gate isolation layer (3), a source/a drain (6) positioned on the etching stopper layer (5) and respectively contacted with two ends of the active layer (4), color filter (8) positioned on the source/the drain (6) and the etching stopper layer (5), and a top gate (9) positioned on the color filter (8) and contacted with the bottom gate (2); the active layer (4) and the thin film of the previous manufacture process can be effectively protected and the original property and the stability of the active layer (4) and the thin film of the previous manufacture process can be ensured.

A device includes a source contact, a drain contact, a gate contact, and a body contact. The body contact is electrically coupled to a temperature sensing circuit. The source contact, the drain contact, the gate contact, and the body contact are included in a fin field-effect transistor (finFET).

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced.

The present invention provides a thin film transistor substrate and a display device that prevent peeling. The thin film transistor substrate includes: an insulating substrate; a thin film transistor; a first inorganic insulating layer; an organic insulating layer stacked on the first inorganic insulating layer; and a second inorganic insulating layer stacked on the organic insulating layer. The organic insulating layer includes a side covered with the second inorganic insulating layer. The first inorganic insulating layer may contain silicon oxide. The organic insulating layer may contain photosensitive resin. The second inorganic insulating layer may contain silicon nitride.