A MEMS chip (100) includes a silicon substrate layer (110), a first oxidation layer (120) and a first thin film layer (130). The silicon substrate layer includes a front surface (112) for a MEMS process and a rear surface (114), both the front surface and the rear surface being polished surfaces. The first oxidation layer is mainly made of silicon dioxide and is formed on the rear surface of the silicon substrate layer. The first thin film layer is mainly made of silicon nitride and is formed on the surface of the first oxidation layer. In the above MEMS chip, by sequentially laminating a first oxidation layer and a first thin film layer on the rear surface of a silicon substrate layer, the rear surface is effectively protected to prevent the scratch damage in the course of a MEMS process. A manufacturing method for the MEMS chip is also provided.

A hermetic package comprising a substrate (110) having a surface with a MEMS structure (101) of a first height (101a), the substrate hermetically sealed to a cap (120) forming a cavity over the MEMS structure; the cap attached to the substrate surface by a vertical stack (130) of metal layers adhering to the substrate surface and to the cap, the stack having a continuous outline surrounding the MEMS structure while spaced from the MEMS structure by a distance (140); the stack having a bottom first metal seed film (131a) adhering to the substrate and a bottom second metal seed film (131b) adhering to the bottom first seed film, both seed films of a first width (131c) and a common sidewall (138); further a top first metal seed film (132a) adhering to the cap and a top second metal seed film (132b) adhering to the top first seed film, both seed films with a second width (132c) smaller than the first width and a common sidewall (139); the bottom and top metal seed films tied to a metal layer (135) including gold-indium intermetallic compounds, layer (135) having a second height (133a) greater than the first height and encasing the seed films and common sidewalls.

There is provided a method for forming a composite cavity and a composite cavity formed using the method. The method comprises the following steps: providing a silicon substrate (101); forming an oxide layer on the front side thereof; patterning the oxide layer to form one or more grooves (103), the position of the groove (103) corresponding to the position of small cavity (109) to be formed; providing a bonding wafer (104), which is bonded to the patterned oxide layer to form one or more closed micro-cavity structures (105) between the silicon substrate (101) and the bonding wafer (104); forming a protective film (106) over the bonding wafer (104) and forming a masking layer (107) on the back side of the silicon substrate (101); patterning the masking layer (107), the pattern of the masking layer (107) corresponding to the position of a large cavity (108) to be formed; using the masking layer (107) as a mask, etching the silicon substrate (101) from the back side until the oxide layer at the front side thereof to form the large cavity (108) in the silicon substrate (101); and using the masking layer (107) and the oxide layer as a mask, etching the bonding wafer (104) from the back side through the silicon substrate (101) until the protective film (106) thereover to form one or more small cavities (109) in the bonding wafer (104). The uniformity of thickness of the semiconductor medium layer where the small cavity (109) in the composite cavity is located is well controlled by the present invention.

There is provided a sensor element including: a semiconductor base member having a first main surface and a second main surface located opposite to the first main surface, and having a cavity structure formed on the second main surface side; and a detection element formed on the first main surface side in a region where the cavity structure is formed, the second main surface of the semiconductor base member including a convexly and concavely shaped portion, and a tip of a convex portion of the convexly and concavely shaped portion having a curved shape.

A hermetic package comprising a substrate (110) having a surface with a MEMS structure (101) of a first height (101a), the substrate hermetically sealed to a cap (120) forming a cavity over the MEMS structure; the cap attached to the substrate surface by a vertical stack (130) of metal layers adhering to the substrate surface and to the cap, the stack having a continuous outline surrounding the MEMS structure while spaced from the MEMS structure by a distance (140); the stack having a bottom first metal seed film (131a) adhering to the substrate and a bottom second metal seed film (131b) adhering to the bottom first seed film, both seed films of a first width (131c) and a common sidewall (138); further a top first metal seed film (132a) adhering to the cap and a top second metal seed film (132b) adhering to the top first seed film, both seed films with a second width (132c) smaller than the first width and a common sidewall (139); the bottom and top metal seed films tied to a metal layer (135) including gold-indium intermetallic compounds, layer (135) having a second height (133a) greater than the first height and encasing the seed films and common sidewalls.

A semiconductor structure includes a first device and a second device. The first device includes a plate including a plurality of apertures; a membrane disposed opposite to the plate and including a plurality of corrugations, and a conductive plug extending through the plate and the membrane. The second device includes a substrate and a bond pad disposed over the substrate, wherein the conductive plug is bonded with the bond pad to integrate the first device with the second device, and the plate includes a semiconductive member and a tensile member, and the semiconductive member is disposed within the tensile member.

For producing a structured coating, or for carefully lifting off a coating over a sensitive region, it is proposed that a release film be applied and structured under the coating in the region which is not to be coated. In a release step, the release film is reduced in the adhesion in the region which is not to be coated and is subsequently lifted off together with the coating applied over it.

Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.

Integrated MEMS-CMOS devices and methods for fabricating MEMS devices and CMOS devices are provided. An exemplary method for fabricating a MEMS device and a CMOS device includes forming the CMOS device in and/or over a first side of a semiconductor substrate. Further, the method includes forming the MEMS device in and/or under a second side of the semiconductor substrate. The second side of the semiconductor substrate is opposite the first side of the semiconductor substrate.

A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer. The steps of forming the bond layer and the protection layer include in-situ deposition of the bond layer and the protection layer.