A capacitive element includes a first conductive layer delimited by an outline and a low voltage dielectric layer covering the first conductive layer. A second conductive layer covers the low voltage dielectric layer and includes: a first portion located over a central zone of the first conductive layer which forms a first capacitor electrode; and a second portion located over the first conductive layer at the inner border of the entire outline of the first conductive layer, and over the front face at the outer border of the entire outline of the first conductive layer. The first portion and the second portion of the second conductive layer are electrically separated by an annular opening extending through the second conductive layer. The first conductive layer is electrically connected to the second portion of the second conductive layer to form a second capacitor electrode.

A manufacturing method of a semiconductor device includes: forming a fin structure; forming a shallow trench isolation structure on the substrate of the fin structure; forming a dummy dielectric layer extending along sidewalls of nanostructures of the fin structure; forming a cladding layer conformally on the dummy dielectric layer; forming a dummy gate layer on the cladding layer; removing a portion of the dummy gate layer by performing an etching process, wherein an etch rate of the cladding layer is higher than an etch rate of the dummy gate layer; forming a gate spacer on the nanostructures of the fin structure, the dummy gate, the cladding layer and the dummy dielectric layer; forming two epitaxial structures coupled to the fin structure; and removing the cladding layer and the dummy dielectric layer before forming a gate metal layer engaging the semiconductor channel layers and located between the two epitaxial structures.

The present disclosure relates to a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device, according to one embodiment, may comprise a gap-fill step of burying a gap-fill oxide in trenches formed on a substrate, so as to form a gap-fill oxide film. In one embodiment, the gap-fill step can comprise a high pressure oxidation (HPO) step. According to embodiments, a semiconductor device with electrical properties superior to those of a conventional semiconductor device can be manufactured.

Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate and a first isolation structure. The substrate has a cell region and a peripheral region. The first isolation structure is disposed in the cell region of the substrate. The first isolation structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is spaced apart from the substrate by the first dielectric layer. The second dielectric layer is doped with an impurity.

A method of manufacturing a semiconductor device includes: performing a first etching operation to form a first trench in a semiconductor substrate; forming a doped region to on a first sidewall of the first trench; performing a second etching operation on the first trench to form a second trench in the semiconductor substrate; depositing a dielectric material in the first and second trenches to form an isolation structure, wherein the isolation structure defines a channel region of the semiconductor device from a top-view perspective; and depositing a dielectric layer on the semiconductor substrate over the doped region and the channel region.

A method for forming a semiconductor device is disclosed herein. The method includes forming a gradient oxide layer on a surface of a substrate, the etch rate of the gradient oxide layer varies along a thickness of the gradient oxide layer, forming a trench through the gradient oxide layer and into the substrate, the trench at least partially defined by a sidewall of the substrate, wherein the surface and the sidewall are connected to form a corner of the substrate, removing a portion of the gradient oxide layer adjacent the corner, wherein a portion of the surface of the substrate is exposed as a result of removing the portion of the gradient oxide layer, and performing an etching process on the exposed corner of the substrate to form a rounded corner that transitions from the surface of the substrate to the sidewall of the substrate.

A semiconductor device structure is provided. The semiconductor device structure includes an isolation feature formed over a substrate that includes a first fin and a second fin separated from each other by the isolation feature. The semiconductor device structure also includes an insulating fin structure formed in the isolation feature between the first fin and the second fin. The insulating fin structure includes a first insulating fin base partially formed within the isolation feature and a first insulating capping layer formed over a top surface of the first insulating fin base.

A method for manufacturing a semiconductor device, the method including forming a fin type pattern including a lower pattern and an upper pattern on a substrate, the upper pattern including a plurality of sacrificial layers and a plurality of sheet patterns alternately stacked on the lower pattern; forming a field insulating film on the substrate and the fin type pattern such that the field insulation film covers side walls of the lower pattern; forming a passivation film on the field insulating film such that the passivation film extends along an upper surface of the field insulating film; and removing the plurality of sacrificial layers after forming the passivation film.

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.