A method of installing a vent to protect an open port of a micro-electrical mechanical system (MEMS) device, the vent being of the type comprising an environmental barrier membrane attached to a carrier and the vent further being attached to a liner, the method comprising the steps of: (a) feeding the vent to a die attach machine with die ejectors and at least one of a vacuum head and a gripper head; (b) detaching the vent from said liner using the die ejectors; (c) picking up the vent with at least one of the vacuum head and the gripper head of the die attach machine; (d) disposing the vent over the open port of the MEMS device; and (e) securing the vent over the open port of the MEMS device.

A MEMS device and a MEMS device manufacturing method are provided for suppressing damage to device parts. An exemplary method of manufacturing a resonance device includes radiating laser light from a bottom surface side of a second substrate to form modified regions inside the second substrate along dividing lines of a first substrate, which has device parts formed on a top surface thereof, and the second substrate, the top surface of which is bonded to the bottom surface of the first substrate via bonding portions. The method further includes dividing the first and second substrates along the dividing lines by applying stress to the modified regions. The bonding portions are formed along the dividing lines and block the laser light.

The MEMS microphone includes a first circuit board; a second circuit board keeping a distance from the first circuit board; a frame located between the first circuit board and the second circuit board for forming a cavity cooperatively with the first circuit board and the second circuit board, the frame including a plated-through-hole; an ASIC chip located in the cavity; and an MEMS chip having a back cavity. The first circuit board is electrically connected with the second circuit board by the plated-through-hole. The frame includes a conductive layer and an insulating layer, and the conductive layer is located between an inner surface of the frame and the insulating layer.

A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.

A method includes forming a front-end-of-the-line (FEOL) element over a substrate; forming a back-end-of-the-line (BEOL) element over the FEOL element; forming an interconnection structure over the substrate; forming a conductive shielding layer electrically connected to the interconnection structure and vertically overlapping the FEOL element and the BEOL element, wherein the conductive shielding layer is grounded to the substrate through the interconnection structure; and forming a dielectric layer covering the conductive shielding layer.

A microelectromechanical structure, including a functional element situated in a cavity of the microelectromechanical structure. The functional element includes an aluminum nitride layer. The cavity is closed by a cap layer. The cap layer includes epitaxial silicon. A method for manufacturing a micromechanical structure is also described.

A MEMS device and a MEMS device manufacturing method are provided for suppressing damage to device parts. An exemplary method of manufacturing a resonance device includes radiating laser light from a bottom surface side of a second substrate to form modified regions inside the second substrate along dividing lines of a first substrate, which has device parts formed on a top surface thereof, and the second substrate, the top surface of which is bonded to the bottom surface of the first substrate via bonding portions. The method further includes dividing the first and second substrates along the dividing lines by applying stress to the modified regions. The bonding portions are formed along the dividing lines and block the laser light.

A process for exposing at least one region of a face, known as the front face, of an electronic device, the process including the following steps: A bonding step for a cover (600) to the front face, the bonding being undertaken such that the cover (600) forms a closed cavity (650) with the region, advantageously hermetically sealed; Formation of an encapsulation coating (700), of thickness E1, covering the front face and the cover (600); A thinning step for the encapsulation coating (700), the thinning step including removal of a removal thickness E2, less than the thickness E1, of the encapsulation coating (700), the removal thickness E2 being adjusted such that an opening is formed in the cover (600).

A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.

A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.