Patent classifications
C04B2235/781
Cubic boron nitride sintered material
A cubic boron nitride sintered material includes: more than or equal to 50 volume % and less than 80 volume % of cubic boron nitride grains; and more than 20 volume % and less than or equal to 50 volume % of a binder phase, and when an oxygen content is measured in a direction perpendicular to an interface between cubic boron nitride grains using TEM-EDX, a first region having an oxygen content larger than an average value of an oxygen content of a cubic boron nitride grain exists, the interface exists in the first region, and a length of the first region along the direction perpendicular to the interface is more than or equal to 0.1 nm and less than or equal to 10 nm.
SPUTTERING TARGET AND METHOD FOR MANUFACTURING THE SAME
A novel metal oxide or a novel sputtering target is provided. A sputtering target includes a conductive material and an insulating material. The insulating material includes an oxide, a nitride, or an oxynitride including an element M1. The element M1 is one or more kinds of elements selected from Al, Ga, Si, Mg, Zr, Be, and B. The conductive material includes an oxide, a nitride, or an oxynitride including indium and zinc. A metal oxide film is deposited using the sputtering target in which the conductive material and the insulating material are separated from each other.
PLASMA-RESISTANT MEMBER
According to an aspect of the invention, there is provided a plasma-resistant member including: a base member; and a layer structural component formed at a surface of the base member, the layer structural component including an yttria polycrystalline body and being plasma resistant, the layer structural component including a first uneven structure, and a second uneven structure formed to be superimposed onto the first uneven structure, the second uneven structure having an unevenness finer than an unevenness of the first uneven structure.
PIEZOELECTRIC MATERIAL COMPOSITION, METHOD OF MANUFACTURING THE SAME, PIEZOELECTRIC DEVICE, AND APPARATUS INCLUDING THE PIEZOELECTRIC DEVICE
A piezoelectric material composition, a method of manufacturing the same, a piezoelectric device, and apparatus including the piezoelectric device. The piezoelectric device may include a piezoelectric device layer including a first material and a second material surrounded by the first material, a first electrode portion disposed at a first surface of the piezoelectric device layer, and a second electrode portion disposed at a second surface of the piezoelectric device layer opposite to the first surface, wherein the piezoelectric device layer comprises a piezoelectric material composition represented by Chemical Formula 1: 0.96(Na.sub.aK.sub.1-a)(Nb.sub.b(T.sub.1-b))O.sub.3-(0.04-x)MZrO.sub.3-x(Bi.sub.cAg.sub.1-c)ZrO.sub.3+d mol % NaNbO.sub.3, wherein T is Sb or Ta, M is Sr, Ba or Ca, a is 0.4≤a≤0.6, b is 0.90≤b≤0.98, c is 0.4≤c≤0.6, d is 0≤d≤5.0, and x is 0≤x≤0.04 and wherein T is Sb or Ta and M is Sr, Ba, or Ca.
Polyimide-based composite carbon film with high thermal conductivity and preparation method therefor
The present invention discloses a polyimide-based composite carbon film with high thermal conductivity and a preparation method therefor. The preparation method includes: uniformly coating the surface of a polyimide-based carbon film with an aqueous graphene oxide solution, and then covering the same with another polyimide-based carbon film uniformly coated with an aqueous graphene oxide solution; repeating such operation; after the polyimide-based carbon films are dried, bonding the polyimide-based carbon films by means of graphene oxide so as to form a thick film; bonding the polyimide-based carbon films more tightly by means of further low-temperature hot pressing; and finally, obtaining a thick polyimide-based carbon film with high thermal conductivity by repairing defects by means of low-temperature heating pre-reduction and high-temperature and high-pressure thermal treatment. The thick polyimide-based carbon film with high thermal conductivity has a thickness greater than 100 μm and an in-plane thermal conductivity of even reaching 1700 W/mK or above.
Dielectric composition and multilayered electronic component comprising the same
A dielectric composition includes a main ingredient having a perovskite structure represented by ABO.sub.3, where A is at least one of Ba, Sr, and Ca and B is at least one of Ti, Zr, and Hf, and a first accessory ingredient. The first accessory ingredient comprises 0.1 mole or more of a rare earth element, 0.02 mole or more of Nb, and 0.25 mole or more and 0.9 mole or less of Mg, a sum of contents of the rare earth element and Nb is 1.5 mole or less.
Rapid pyrolysis to form super ionic conducting lithium garnets
A method of preparing a lithium-ion conducting garnet via low-temperature solid-state synthesis is disclosed. The lithium-ion conducting garnet comprises a substantially phase pure aluminum-doped cubic lithium lanthanum zirconate (Li.sub.7La.sub.3Zr.sub.2O.sub.14). The method includes preparing nanoparticles comprising lanthanum zirconate (La.sub.2Zr.sub.2O.sub.7-np) via pyrolysis-mediated reaction of lanthanum nitrate (La(NO.sub.3).sub.3) and zirconium nitrate (Zr(NO.sub.3).sub.4). The method also includes pyrolyzing a solid-state mixture comprising the La.sub.2Zr.sub.2O.sub.7-np, lithium nitrate (LiNO.sub.3), and aluminum nitrate (Al(NO.sub.3).sub.3) to give the Li.sub.7La.sub.3Zr.sub.2O.sub.14 and thereby prepare the lithium-ion conducting garnet. A lithium-ion conducting garnet prepared via the method is also disclosed.
Ceramic
The present invention relates to a ceramic, to a process for preparing the ceramic and to the use of the ceramic as a dielectric in a capacitor.
Multi-layer ceramic capacitor and method of producing the same
A multi-layer ceramic capacitor includes: a first region including a polycrystal including, as a main component, crystal grains free from intragranular pores; a second region that includes a polycrystal including, as a main component, crystal grains including intragranular pores and includes a higher content of silicon than a content of silicon in the first region; a capacitance forming unit including ceramic layers laminated along a first direction, and internal electrodes disposed between the ceramic layers; and a protective portion including a cover that covers the capacitance forming unit and constitutes a main surface facing in the first direction, a side margin constituting a side surface facing in a second direction orthogonal to the first direction, and a ridge constituting a connection portion, the connection portion connecting the main surface and the side surface to each other. The ceramic layers include the first region. The ridge includes the second region.
CERAMIC ELECTRONIC DEVICE AND MANUFACTURING METHOD OF THE SAME
A ceramic electronic device includes a multilayer structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked, a main component of the plurality of dielectric layers being a ceramic having a perovskite structure expressed by a general formula ABO.sub.3. At least one of crystal grains of the plurality of dielectric layers has a core-shell structure. A dispersion of atomic displacement amounts between B site atoms and oxygen atoms of a shell of the core-shell structure is larger than a dispersion of atomic displacement amounts between B site atoms and oxygen atoms of a core of the core-shell structure.