Patent classifications
C30B29/40
Semiconductor Phosphide Injection Synthesis System and Control Method
A semiconductor phosphide injection synthesis system and a control method are provided, which belong to the technical field of preparation of semiconductor phosphides. The semiconductor phosphide injection synthesis system includes a furnace body, a shielding carrier box arranged above the furnace body by virtue of a lifting mechanism, a phosphorus source carrier arranged in the shielding carrier box, an injection pipe arranged below the phosphorus source carrier, and a crucible arranged at an inner bottom of the furnace body in a matched manner. The phosphorus source carrier includes a phosphorus source carrier main body, a phosphorus source carrier upper cover, a heating element base arranged at an inner bottom of the phosphorus source carrier main body, and a heating element arranged on the heating element base; a heat insulation layer is wrapped on an outer wall of the phosphorus source carrier; and an induction coil is arranged between the heat insulation layer and an inner wall of the shielding carrier box. By improving a device and method, the system stability can be improved, and an entire synthesis system achieves quantitative synthesis, which lowers the risk of explosion of the phosphorus source carrier.
Thermal control for formation and processing of aluminum nitride
In various embodiments, controlled heating and/or cooling conditions are utilized during the fabrication of aluminum nitride single crystals and aluminum nitride bulk polycrystalline ceramics. Thermal treatments may also be utilized to control properties of aluminum nitride crystals after fabrication.
Rocking type seed crystal surface corrosion, cleaning and drying device and process method
A rocking type seed crystal surface corrosion, cleaning and drying device and a process method belong to the technical field of semiconductor crystal growth, comprising a corrosion tank and a matched corrosion tank cover, a seed crystal support platform arranged at a middle position of the bottom of the corrosion tank, and a high-purity hot nitrogen introduction short straight pipe, an corrosive liquid introduction short straight pipe, a deionized water introduction short straight pipe and an overflow liquid discharge short straight pipe matched with and arranged at both sides of the corrosion tank, wherein free ends of the high-purity hot nitrogen introduction short straight pipe, the corrosive liquid introduction short straight pipe and the deionized water introduction short straight pipe are all provided with switch stop valves; the device further comprises a rocking mechanism provided at the bottom of the corrosion tank; and the seed crystal support platform comprises a support frame symmetrically distributed on both sides of the vertical central axis of the corrosion tank and positioned at the bottom of the corrosion tank, a seed crystal support wheel mounted on an upper end of the support frame via a rotating shaft, and a matched seed crystal support wheel limiting mechanism. Adequate corrosion can be performed on the entire seed crystal surface, and the cleaning and drying processes of the seed crystal in the subsequent process can be combined organically to avoid secondary contamination of the seed crystal in the subsequent process.
Rocking type seed crystal surface corrosion, cleaning and drying device and process method
A rocking type seed crystal surface corrosion, cleaning and drying device and a process method belong to the technical field of semiconductor crystal growth, comprising a corrosion tank and a matched corrosion tank cover, a seed crystal support platform arranged at a middle position of the bottom of the corrosion tank, and a high-purity hot nitrogen introduction short straight pipe, an corrosive liquid introduction short straight pipe, a deionized water introduction short straight pipe and an overflow liquid discharge short straight pipe matched with and arranged at both sides of the corrosion tank, wherein free ends of the high-purity hot nitrogen introduction short straight pipe, the corrosive liquid introduction short straight pipe and the deionized water introduction short straight pipe are all provided with switch stop valves; the device further comprises a rocking mechanism provided at the bottom of the corrosion tank; and the seed crystal support platform comprises a support frame symmetrically distributed on both sides of the vertical central axis of the corrosion tank and positioned at the bottom of the corrosion tank, a seed crystal support wheel mounted on an upper end of the support frame via a rotating shaft, and a matched seed crystal support wheel limiting mechanism. Adequate corrosion can be performed on the entire seed crystal surface, and the cleaning and drying processes of the seed crystal in the subsequent process can be combined organically to avoid secondary contamination of the seed crystal in the subsequent process.
PREPARATION METHOD FOR SEMICONDUCTOR STRUCTURE
Disclosed is a preparation method for a semiconductor structure. The semiconductor structure includes: a substrate; an epitaxial layer and an epitaxial structure that are stacked on the substrate in sequence. The epitaxial layer is doped with a doping element. In the forming process, a sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that a concentration of the doping element in the epitaxial layer is lower than a preset value. In this application, the sacrificial layer is formed on the epitaxial layer, and the sacrificial layer is repeatedly etched, such that the concentration of the doping element in the epitaxial layer is lower than the preset value, so as to prevent the doping element in the epitaxial layer from being precipitated upward into an upper-layer structure, ensure the mobility of electrons in a channel layer, and improve the performance of a device.
Method and structure of single crystal electronic devices with enhanced strain interface regions by impurity introduction
A method of manufacture and resulting structure for a single crystal electronic device with an enhanced strain interface region. The method of manufacture can include forming a nucleation layer overlying a substrate and forming a first and second single crystal layer overlying the nucleation layer. This first and second layers can be doped by introducing one or more impurity species to form a strained single crystal layers. The first and second strained layers can be aligned along the same crystallographic direction to form a strained single crystal bi-layer having an enhanced strain interface region. Using this enhanced single crystal bi-layer to form active or passive devices results in improved physical characteristics, such as enhanced photon velocity or improved density charges.
Group 13 element nitride layer, free-standing substrate and functional element
A layer of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride and the mixed crystals thereof has an upper surface and a bottom surface. The upper surface includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part. The high-luminance light-emitting part includes a portion extending along an m-plane of the crystal of the group 13 nitride. A normal line to the upper surface has an off-angle of 2.0° or less with respect to <0001> direction of the crystal of the nitride of the group 13 element.
GaN single crystal and method for manufacturing GaN single crystal
A GaN single crystal having a gallium polar surface which is a main surface on one side and a nitrogen polar surface which is a main surface on the opposite side, wherein on the gallium polar surface is found at least one square area, an outer periphery of which is constituted by four sides of 2 mm or more in length, and, when the at least one square area is divided into a plurality of sub-areas each of which is a 100 μm×100 μm square, pit-free areas account for 80% or more of the plurality of sub-areas.
MANUFACTURE OF GROUP IIIA-NITRIDE LAYERS ON SEMICONDUCTOR ON INSULATOR STRUCTURES
A method is provided for forming Group IIIA-nitride layers, such as GaN, on substrates. The Group IIIA-nitride layers may be deposited on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates. The Group IIIA-nitride layers may be deposited by heteroepitaxial deposition on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates.
TECHNIQUE FOR THE GROWTH AND FABRICATION OF SEMIPOLAR (Ga,Al,In,B)N THIN FILMS, HETEROSTRUCTURES, AND DEVICES
A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.