A test board for testing a semiconductor apparatus includes a first board configured to support a plurality of first Devices Under Test (DUTs) such that the plurality of first DUTs are mounted on the first board, a plurality of first inter-board connectors arranged on the first board, and a plurality of second boards stacked on the first board through the plurality of first inter-board connectors, each second board of the plurality of second boards having a surface configured to support a separate second DUT of a plurality of second DUTs such that the plurality of second DUTs are mounted on separate, respective second boards of the plurality of second board.

A probe card and a probe module thereof are provided. The probe card includes a first strengthening board, a fixed frame, a probe module, and a slidable frame. The first strengthening board includes a top surface, a bottom surface, and a mounting hole. An inner wall of the mounting hole is formed with an inner flange. The fixed frame is disposed on the top surface of the first strengthening board and surrounds the mounting hole. The probe module is disposed in the mounting hole and includes an outer flange including a physical region and multiple gap regions. The physical region abuts against the inner flange of the first strengthening board. The slidable frame is disposed on an inner wall of the fixed frame and is slidable between a released position and a fixed position. Multiple pressing portions are disposed on an inner wall of the slidable frame.

A method of detecting abnormalities includes: calculating a reference failure rate using failure data at a plurality of points in time included in a particular period; calculating a detection failure rate and weighting, corresponding to failure data at a detection time point after the particular period, using the reference failure rate; calculating an abnormality index based on multiplying the detection failure rate by the weighting; comparing the abnormality index with an index corresponding to a control limit for stably controlling a failure rate; and detecting whether the failure data at the detection time point is abnormal, based on a result of the comparison of the abnormality index with the index corresponding to the control limit.

A tester apparatus is described. Various components contribute to the functionality of the tester apparatus, including an insertion and removal apparatus, thermal posts, independent gimbaling, the inclusion of a photo detector, a combination of thermal control methods, a detect circuitry in a socket lid, through posts with stand-offs, and a voltage retargeting.

Disclosed is a probe card for testing a wafer. The probe card includes a substrate and a block including an insulation portion and a conducting portion disposed on the insulation portion. Here, the insulation portion includes a via and a probe pin which comes into contact with an object to be tested. The conducting portion includes a contact point electrically connected to the substrate and a conducting pattern passing through the via and electrically connecting the contact point to the probe pin. A pitch between a plurality of such probe pins is smaller than a pitch between a plurality of such contact points. The block includes a plurality of unit blocks. The plurality of unit blocks each include the insulation portion and the conducting portion, and at least parts of the insulation portions of the unit blocks are arranged while being spaced apart from each other.

Provided is a two axis test fixture, which can include systems and associated methods. Some methods described also include implementing and/or controlling a two-axis test fixture. Systems and computer program products are also provided. A test fixture is used to test, calibrate, or validate an IMU. The test fixture is operable to rotate a device under test (e.g., IMU) along two axes while mounted to a turntable. The rotation of the turntable is enabled via multiple slip rings, rotational bearings, and standoff fixtures. Testing of the device along greater than two axes is achieved through rotation of the device under test on the turntable, and revolutions of the device under test about an axle.

A wafer inspection system is provided. The wafer inspection system includes: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.

A tester apparatus is described. Various components contribute to the functionality of the tester apparatus, including an insertion and removal apparatus, thermal posts, independent gimbaling, the inclusion of a photo detector, a combination of thermal control methods, a detect circuitry in a socket lid, through posts with stand-offs, and a voltage retargeting.

A wafer chip testing method and apparatus, an electronic device and a storage medium are provided. The testing method includes: comparing each configuration parameter of each wafer chip with a standard specification threshold interval of a corresponding parameter type, and marking as marked test parameters configuration parameters which do not belong to the standard specification threshold intervals; and inputting all marked test parameters of individual wafer chip into a combination rule judgment function respectively, outputting wafer chip(s) which does not conform to any one or more rules in the combination rule judgment function, and determining the wafer chip(s) as unqualified wafer chip(s).

A calibration method includes transmitting first data comprising a calibration data and a first checksum to the storage device according to each of a plurality of training parameter sets; recording a plurality of error indicators respectively which are corresponding to the plurality of training parameter sets and from the storage device; and identifying one of the plurality of training parameter sets as a predetermined parameter set according to the plurality of error indicators respectively corresponding to the plurality of training parameter sets; wherein each error indicator indicates whether transmitting the first data according to the corresponded training parameter set is successful.