A measurement device (10) includes a first processor (12a) that performs first pipeline processing on a first input signal according to a first sample timing, a second processor (12b) that performs second pipeline processing on a second input signal according to a second sample timing with a sampling period longer than the first sample timing, an adjustment unit that adjusts an output timing of the first input signal on which the first pipeline processing was performed to match an output timing of the second input signal on which the second pipeline processing was performed, and a creation unit (17) that sequentially creates a waveform of the first input signal on which the first pipeline processing was performed and for which the output timing was adjusted by the adjustment unit, and a waveform of the second input signal on which the second pipeline processing was performed.

A test and measurement instrument has a user interface configured to allow a user to provide one or more user inputs, a display to display results to the user, a memory, one or more processors configured to execute code to cause the one or more processors to receive a waveform array containing waveforms resulting from sweeping one or more parameters from a set of parameters, recover a clock signal from the waveform array, generate a waveform image for each waveform, render the waveform images into video frames to produce an image array of the video frames, select at least some of the video frames to form a video sequence, and play the video sequence on a display. A method of animating waveform data includes receiving a waveform array containing waveforms resulting from sweeping one or more parameters from a set of parameters, recovering a clock signal from the waveforms, generating a waveform image from each of the waveforms, rendering the waveform images into video frames to produce an image array of the video frames, selecting at least some of the video frames to play as a video sequence, and playing the video sequence on a display.

A system and method are provided for displaying input signals from a DUT on a display screen. The method includes sending a data stream of digitized data received from the DUT to an FPGA for serial decoding; receiving decoded symbols from the FPGA; identifying valid symbols among the decoded symbols indicating transitions between the decoded symbols; storing the valid symbols with corresponding time-tags as valid packets in memory, and discarding ones of the decoded symbols occurring between the valid symbols; and plotting on the display screen the valid packets occurring between beginning and ending valid packets of the stored valid packets. The beginning valid packet has a corresponding time-tag occurring immediately before a first point time-tag associated with a left edge of the display screen, and the ending valid packet has a corresponding time-tag occurring at or immediately before a last point time-tag associated with a right edge of the display screen.

Methods of triggering a test and measurement instrument having a plurality of inputs include the step of generating a trigger signal in response to every occurrence of any one of a plurality of specified trigger events. A first specified trigger event occurs in at least a first one of the inputs and a second specified trigger event occurs in at least a second one of the plurality of inputs. A specified trigger event may include at least one selected input from the plurality of inputs and a selected activity type. Some methods include configuring each of a plurality of event activity detectors to produce a pulse in a logic signal in response to every occurrence of one of the specified trigger events. The plurality of logic signals are combined in a logical OR circuit to generate the trigger signal. Trigger circuits configured according to these methods are also disclosed.

A test and measurement device includes an input port to receive an input signal, a sampling circuit structured to generate a sample from the input signal, in which generating the sample from the input signal produces an amount of kickout energy, and an energy reducing circuit coupled between the sampling circuit and one or more other components of the test and measurement device, the energy reducing circuit structured to decrease the amount of kickout energy from the sampling circuit. The energy reducing circuit may include or be combined with a pick-off circuit. Methods are also described.

The disclosure relates to a test and measurement instrument. The test and measurement instrument comprises a digitizer for digitizing an analog input signal, thereby generating a digitized input signal. The test and measurement instrument also has a digital trigger for detecting a trigger event in the digitized input signal. The test and measurement instrument also comprises an acquisition memory for acquiring the digitized input signal at least segmentally upon a first trigger event detected by the digital trigger. The acquisition memory is configured to acquire a first signal segment prior to the first trigger event. The acquisition memory is further configured to acquire a second signal segment starting at the first trigger event. The length of the second signal segment is dynamically adjustable. Moreover, a method of analyzing an input signal by a test and measurement instrument is described.

A test and measurement instrument includes a first data channel including a first data converter operating at a first rate, and a second data channel including a second data converter operating at a second rate that is different than the first rate. Rate controls may include a clock generation circuit. The clock generation circuit includes an intermediate frequency generator structured to generate an intermediate frequency clock from a first clock reference signal, a first frequency clock generator structured to generate a first frequency clock directly from the intermediate frequency clock, and a second frequency clock generator structured to generate a second frequency clock directly from the intermediate frequency clock. The first frequency clock may be used to control the rate of the first data channel, and the second frequency clock may be used to control the rate of the second data channel. Methods are also described.

Provided are an automatic trigger type identification method and device and an oscilloscope, which belong to the field of oscilloscopes. The method includes analyzing characteristic parameter data of a to-be-triggered signal. The characteristic parameter data comprises at least one of bus protocol matching information or variation information of at least one characteristic parameter. In this way, a trigger type capable of stably triggering the to-be-triggered signal can be obtained for user selection or automatic selection for trigger.

An oscilloscope includes a signal input circuit, a switching matrix circuit, and a downconverter circuit. The signal input circuit is configured to receive M input signals, wherein at least one of the input signals is a signal comprising at least two carriers. The switching matrix circuit is configured to selectively forward at least one input signal from at least one of the switching matrix inputs to the switching matrix outputs. The downconverter circuit includes a local oscillator and at least two downconverter sub-circuits. The at least two downconverter sub-circuits are configured, for example, to: down-convert a first signal component of the signal that is associated with a first one of the least two carriers based on a local oscillator signal and down-convert a second signal component of the signal that is associated with a second one of the least two carriers based on the local oscillator signal, respectively.

A test and measurement instrument includes an auxiliary trigger input port for receiving an auxiliary trigger signal, a digital trigger processor for generating a digital trigger signal from the auxiliary trigger signal, an analog trigger processor for generating an analog trigger signal from the auxiliary trigger signal, a user-configurable selector coupled to the digital trigger processor and to the analog trigger processor, the user-configurable selector configured to output either the digital trigger signal or the analog trigger signal as a selected trigger output signal of the instrument. Methods of creating parallel triggers are also described.