A test and measurement device is described with at least one measurement channel, a measurement input, an analog to digital converter, and an acquisition unit. The test and measurement device has a trigger clock configured to generate repeated trigger clock timings, the trigger clock timings controlling the acquisition unit. In addition, a method for applying a trigger is described.

A test and measurement system includes a clock recovery circuit configured to receive a signal from a device under test and to produce a pattern trigger signal, a flash array digitizer having an array of counters having rows and columns configured to store a waveform image representing the signal received from the device under test, a row selection circuit configured to select a row in the array of counters, and a ring counter circuit configured to receive a clock signal, select a column in the array of counters, produce end of row signals, and produce a fill complete signal upon all of the columns having been swept, the fill complete signal indicating completion of the waveform image, an equivalent time sweep logic circuit configured to receive the pattern trigger signal and the end of row signals from the ring counter and to produce the clock signal with a delay to increment a clock delay to the ring counter until the fill complete signal is received, and a machine learning system configured to receive the waveform image and provide operating parameters for the device under test. A test and measurement system includes a flash array digitizer having an array of counters having rows and columns configured to store a waveform image representing a signal received from a device under test, a row selection circuit configured to select a row in the array of counters, a column selection circuit configured to select a column in the array of counters, a sample clock connected to the row selection circuit and the column selection circuit, and a machine learning system configured to receive the waveform image from the flash array digitizer and provide operating parameters for the device under test.

A measurement device is described that comprises a measurement unit configured to perform measurements on an electric signal of a device under test while applying at least one measurement parameter for performing the measurements. The measurement device has an integrated direct current source configured to power the device under test. The measurement device also comprises a monitoring unit configured to monitor at least one monitoring parameter of the direct current source. The measurement device has a control unit configured to control the measurement parameter. Further, a method for measuring a device under test is described.

A circuit and a method for reducing interference of power on/off to hardware test. The circuit includes: a power unit, a voltage processing unit, a PSU and a to-be-tested hardware. An input terminal of the voltage processing unit is connected to the power unit, an output terminal of the voltage processing unit is connected to an input terminal of the PSU, and an output terminal of the PSU is connected to the to-be-tested hardware; the power unit is configured to provide an operating voltage; the voltage processing unit is configured to eliminate electric sparks caused by instability of the operating voltage at an instant of power on/off; the PSU is configured to convert a stable operating voltage outputted from the voltage processing unit into a direct current voltage required for the to-be-tested hardware; and the to-be-tested hardware is configured to receive the direct current voltage outputted from the PSU.

Embodiments of the invention include methods and instruments for performing combinatorial mask triggering. One or more mask triggers can be configured. Combinatorial mask triggering logic can make various determinations about the relationship between a digitized signal and the one or more mask triggers. The various determinations about the relationship can include considerations of both space and time. When the combinatorial trigger criteria have been satisfied, a trigger signal is generated, and the digital data associated with an incoming signal is stored to memory. The combinatorial mask triggering logic can operate on signals in the frequency domain, the time domain, or both.

The present disclosure provides a main measurement device for simultaneously measuring signals with at least one secondary measurement device, the main measurement device comprising a reference signal output port configured to couple to the at least one secondary measurement device, a reference signal generator coupled to the reference signal output port and configured to generate a reference signal, a measurement port configured to receive a signal to be measured, a trigger output port configured to couple to a trigger input port of the at least one secondary measurement device and to output a trigger signal, and a controllably switchable internal signal path configured to selectively couple the reference signal generator with the measurement port. Further, the present invention discloses a respective secondary measurement device, a respective measurement system, and a respective method.

A system and method are provided for graphically actuating a trigger in a test and measurement device. The method includes displaying a visual representation of signal properties for one or more time-varying signals. A graphical user input is received, in which a portion of the visual representation is designated. The method further includes configuring a trigger of the test and measurement device in response to the graphical user input, by setting a value for a trigger parameter of the trigger. The set value for the trigger parameters varies with and is dependent upon the particular portion of the visual representation that is designated by the graphical user input. The trigger is then employed in connection with subsequent monitoring of signals within the test and measurement device.

A method of analyzing a signal is described. The method includes: setting a trigger condition to be applied; applying the trigger condition; acquiring at least two acquisitions associated with the input signal, each acquisition including a trigger event that matches the trigger condition set; determining a trigger time for each trigger event; storing a time stamp with each trigger event; and generating a histogram based on the time stamps stored, the histogram providing number of trigger events versus time. Further, a signal analysis device for analyzing a signal is described.

A signal acquisition circuit for acquiring data of an input signal comprising at least n acquisition units, wherein n is integer greater than one, the n acquisition units comprising k inputs, wherein k is integer greater than one, and wherein at least two inputs are assigned to one channel and the corresponding acquisition units run time interleaved, and at least one trigger unit, wherein the number 1 of the at least one trigger unit is integer and wherein 1 is smaller than k. Further, a single-housed device as well as a method of acquiring data of an input signal are described.

A deskew fixture includes first and second deskew probe points for contacting first and second probes, respectively, during deskew calibration, a signal generating circuit for generating a calibration signal provided to the first and second deskew probe points, and a feedback loop for automatically self-calibrating the deskew fixture. The feedback loop includes first and second analog to digital converters (ADCs) for digitizing the calibration signal at the first and second deskew probe points while contacting the first and second probes, respectively, to provide first and second digitized calibration signals, and a processing unit programmed to determine inherent skew of the deskew fixture between the first and second skew probe points using the first and second digitized calibration signals, and to provide the determined inherent skew to a test instrument for use in the deskew calibration of the first and second probes.