Measurement apparatus and method for digital data acquisition. A first operation mode is provided for real-time processing of digital data having a reduced sample rate or resolution. Furthermore, a second operation mode is provided for processing the measurement signal off-line with a higher accuracy. In particular, the high accuracy data may be temporarily stored and analyzed upon the operation mode is changed from the real-time mode to the off-line mode.

A system and method are provided for displaying input signals from a DUT on a display screen. The method includes sending a data stream of digitized data received from the DUT to an FPGA for serial decoding; receiving decoded symbols from the FPGA; identifying valid symbols among the decoded symbols indicating transitions between the decoded symbols; storing the valid symbols with corresponding time-tags as valid packets in memory, and discarding ones of the decoded symbols occurring between the valid symbols; and plotting on the display screen the valid packets occurring between beginning and ending valid packets of the stored valid packets. The beginning valid packet has a corresponding time-tag occurring immediately before a first point time-tag associated with a left edge of the display screen, and the ending valid packet has a corresponding time-tag occurring at or immediately before a last point time-tag associated with a right edge of the display screen.

A test and measurement device includes an input port to receive an input signal, a sampling circuit structured to generate a sample from the input signal, in which generating the sample from the input signal produces an amount of kickout energy, and an energy reducing circuit coupled between the sampling circuit and one or more other components of the test and measurement device, the energy reducing circuit structured to decrease the amount of kickout energy from the sampling circuit. The energy reducing circuit may include or be combined with a pick-off circuit. Methods are also described.

An oscilloscope includes a signal input circuit, a switching matrix circuit, and a downconverter circuit. The signal input circuit is configured to receive M input signals, wherein at least one of the input signals is a signal comprising at least two carriers. The switching matrix circuit is configured to selectively forward at least one input signal from at least one of the switching matrix inputs to the switching matrix outputs. The downconverter circuit includes a local oscillator and at least two downconverter sub-circuits. The at least two downconverter sub-circuits are configured, for example, to: down-convert a first signal component of the signal that is associated with a first one of the least two carriers based on a local oscillator signal and down-convert a second signal component of the signal that is associated with a second one of the least two carriers based on the local oscillator signal, respectively.

A voltage monitoring circuit is disclosed. An apparatus includes a first physical interface circuit and a real-time oscilloscope circuit configured to monitor a first voltage provided to the first physical interface circuit. The real-time oscilloscope is configured to receive an indication that an error was detected in data transmitted from the first physical interface to a second physical interface circuit. The real-time oscilloscope is further configured to provide for debug, to a host computer external to the first interface, information indicating a state of the first voltage at a time at which the error was detected.

A method for recovering data included in a digitally modulated signal is described. The digitally modulated signal includes a symbol sequence. The method includes providing a mathematical model of the digitally modulated signal, the mathematical model describing the digitally modulated signal in terms of the symbol sequence and describing the digitally modulated signal in terms of a step response and/or an impulse response, and wherein the mathematical model also takes disturbances into account; and processing the digitally modulated signal based on the mathematical model, thereby recovering the data included in the digitally modulated signal. The disturbances include a random disturbance component modelled as a Gaussian disturbance, and include an inter-symbol interference component modelled as Gaussian noise, and wherein a dependence of the at least one step response on the symbol sequence is neglected within the mathematical model. Further, a measurement instrument and a measurement system are described.

A measurement instrument for acquiring an input signal is described. The measurement instrument includes a first acquisition path with a first acquisition circuit having a first sampling rate. The measurement instrument includes at least one second acquisition path with a second acquisition circuit, having a second sampling rate. The measurement instrument is configured to acquire the input signal with an overall sampling rate being higher than the first sampling rate and the second sampling rate. The first acquisition path and the at least one second acquisition path each have a decimation filter and a decimator connected in series to the decimation filter, thereby equalizing a low frequency band in the input signal when processing the input signal. Further, method of acquiring an input signal is described.

A test and measurement device has an input port configured to receive a signal from a device under test, the signal having a symbol rate, one or more analog-to-digital converters to convert the signal to waveform samples at a sampling rate, and one or more processors configured to execute code that, when aliasing is present in the waveform samples, causes the one or more processors to: up-sample the waveform samples to produce up-sampled samples; use the up-sampled samples to produce a real-time waveform; perform clock recovery on the real-time waveform to produce a recovered clock; and resample the waveform samples using the recovered clock to produce a non-aliased waveform. A method of acquiring a waveform in a test and measurement device includes receiving a signal from a device under test, the signal having a symbol rate, converting the signal to waveform samples at a sampling rate of the test and measurement device, when aliasing is present in the waveform samples, up-sampling the waveform samples to produce up-sampled samples, using the up-sampled samples to produce a real-time waveform, performing clock recovery on the real-time waveform to produce a recovered clock, and resampling the waveform samples using the recovered clock to produce a non-aliased waveform.

A method, a system, and a computer program for executing high resolution spectrum monitoring. A sensor receives an input signal having a varying frequency content over time. One or more samples of the received input signal are sampled. The samples of the received input signal include one or more swept signal samples generated by sweeping, using a center frequency of the sensor, the received input signal across an entire frequency spectrum associated with the received input signal. Sampling of the samples of the received signal is performed while performing the sweeping. The signal samples are processed.

A test and measurement system includes a clock recovery circuit configured to receive a signal from a device under test and to produce a pattern trigger signal, a flash array digitizer having an array of counters having rows and columns configured to store a waveform image representing the signal received from the device under test, a row selection circuit configured to select a row in the array of counters, and a ring counter circuit configured to receive a clock signal, select a column in the array of counters, produce end of row signals, and produce a fill complete signal upon all of the columns having been swept, the fill complete signal indicating completion of the waveform image, an equivalent time sweep logic circuit configured to receive the pattern trigger signal and the end of row signals from the ring counter and to produce the clock signal with a delay to increment a clock delay to the ring counter until the fill complete signal is received, and a machine learning system configured to receive the waveform image and provide operating parameters for the device under test. A test and measurement system includes a flash array digitizer having an array of counters having rows and columns configured to store a waveform image representing a signal received from a device under test, a row selection circuit configured to select a row in the array of counters, a column selection circuit configured to select a column in the array of counters, a sample clock connected to the row selection circuit and the column selection circuit, and a machine learning system configured to receive the waveform image from the flash array digitizer and provide operating parameters for the device under test.