A method for checking quality when resistance-welding workpiece includes pressing welding electrodes with an electrode force against a weld spot of the workpieces using an electrode drive and energizing the welding electrodes with a welding current for a duration of a welding time in order to liquefy a surface of the workpieces. The method further includes determining, at a first time before a beginning of the liquefaction, a first value of a welding electrode parameter identifying a position of one or both electrodes, and determining, at a second time after the beginning of the liquefaction, a second value of the welding electrode parameter identifying a position of one or both electrodes. The method further includes comparing the first value and the second value and, evaluating a quality of the welding process based on the comparison.

A method for checking quality when resistance-welding workpiece includes pressing welding electrodes with an electrode force against a weld spot of the workpieces using an electrode drive and energizing the welding electrodes with a welding current for a duration of a welding time in order to liquefy a surface of the workpieces. The method further includes determining, at a first time before a beginning of the liquefaction, a first value of a welding electrode parameter identifying a position of one or both electrodes, and determining, at a second time after the beginning of the liquefaction, a second value of the welding electrode parameter identifying a position of one or both electrodes. The method further includes comparing the first value and the second value and, evaluating a quality of the welding process based on the comparison.

A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

An apparatus according to an embodiment includes a control circuit to control operations of an inverter and a switch. The control circuit judges whether or not a power system has a power failure, based on values of the system voltage and a frequency of the power system; and calculates a phase difference between a phase of the output voltage of the inverter and a phase of the system voltage and generate, by means of the phase difference, an output frequency pattern for changing a frequency of the output voltage of the inverter. The control circuit, when it is judged that the power system has recovered from the power failure, controls the inverter to change the frequency of the output voltage of the inverter in line with the output frequency pattern, and closes the switch after the phase difference becomes smaller than or equal to a threshold.

An apparatus according to an embodiment includes a control circuit to control operations of an inverter and a switch. The control circuit judges whether or not a power system has a power failure, based on values of the system voltage and a frequency of the power system; and calculates a phase difference between a phase of the output voltage of the inverter and a phase of the system voltage and generate, by means of the phase difference, an output frequency pattern for changing a frequency of the output voltage of the inverter. The control circuit, when it is judged that the power system has recovered from the power failure, controls the inverter to change the frequency of the output voltage of the inverter in line with the output frequency pattern, and closes the switch after the phase difference becomes smaller than or equal to a threshold.

Circuit arrangement via which a voltage type and value of an input voltage of a. power supply or a switching-mode power supply is ascertained is configured such that the input voltage of the power supply decreases at the input side and includes a differential amplifier for converting the input voltage into a signal rectified by a first rectifier such that a forward voltage of the first rectifier is compensated, includes an inverter which generates an inverted signal rectified by a second rectifier such that a forward voltage of the second rectifier is compensated, includes a mixer via which a first output signal is generated from the useful signals, from which first output signal a second output signal is derived via a filter such that the voltage type is determinable from the first output signal, and a voltage value of the input voltage can be determined from the second output signal.

A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.

Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.

Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.

A method of determining the orientation of a device having disposed therein, in part, an inertia measurement unit, a phased array receiver, and a controller, includes, in part, detecting the difference between phases of an RF signal received by at least a pair of receive elements of the phased array receiver, determining the angle of incidence of the RF signal from the phase difference, using the angle of incidence to determine the projection of a vector on a plane of an array of transmitters transmitting the RF signal, and determining the yaw of the device from the projection of the vector. The vector is a three-dimensional vector representative of the orientation of the plane of the phased array receivers relative to the plane of the array of transmitters transmitting the RF signal.