According to one embodiment, a sensor includes an element part, and a control circuit part. The element part includes first and second elements. Each of the first and second elements includes a first magnetic element and a first conductive member. The control circuit part includes a first current circuit, a differential circuit, and a phase detection circuit. The first current circuit is configured to supply a first current to the first conductive member. The differential circuit is configured to output a differential signal corresponding to a difference of a first signal and a second signal. The first signal corresponds to a change in a first electrical resistance of the first magnetic element of the first element, The second signal corresponds to a change in a second electrical resistance of the first magnetic element of the second element. The phase detection circuit is configured to perform a phase detection of the differential signal.

An impedance sensing circuit includes first and second current sources and first and second bias current sources that are appropriately coupled to first and second resistors. The impedance sensing circuit also includes a comparator that compares a first voltage based on the first terminal of the first resistor to a second voltage based on the first terminal of the second resistor to generate a comparator output signal. Either the comparator output signal or a digital signal based on the comparator output signal operates to regulate the current signals output from the first and second current sources so that the first voltage is same as the second voltage. The comparator output signal and the digital signal is representative of a difference between the first voltage and the second voltage that is based on an impedance difference between the first resistor and the second resistor.

A test structure for a buried gate transistor includes a substrate, a first test contact located on one side of a first transistor contact, a second test contact located on one side of a second transistor contact, and a layer buried in the substrate, having a doping greater than or equal to 10.sup.18 cm.sup.−3, and having a face which is tangent to the buried part of the gate. A first insulation structure is disposed between the first test contact and the first transistor contact and a second insulation structure is disposed between the second test contact and the second transistor contact. The first and second test contacts each have an end connected to the buried layer.

According to one embodiment, a sensor includes an element part, and a control circuit part. The element part includes first and second elements. Each of the first and second elements includes a first magnetic element and a first conductive member. The control circuit part includes a first current circuit, a differential circuit, and a phase detection circuit. The first current circuit is configured to supply a first current to the first conductive member. The differential circuit is configured to output a differential signal corresponding to a difference of a first signal and a second signal. The first signal corresponds to a change in a first electrical resistance of the first magnetic element of the first element. The second signal corresponds to a change in a second electrical resistance of the first magnetic element of the second element. The phase detection circuit is configured to perform a phase detection of the differential signal.

A sensor arrangement includes a switchable voltage source having a source output for alternatively providing a first and a second excitation voltage, an integrator having an integrator input and an integrator output, a sensor resistor having a first terminal coupled to the source output, a reference resistor having a first terminal coupled to a second terminal of the sensor resistor and a second terminal coupled to the integrator input, and a comparator having a first comparator input coupled to the integrator output.

A sensor arrangement includes a switchable voltage source having a source output for alternatively providing a first and a second excitation voltage, an integrator having an integrator input and an integrator output, a sensor resistor having a first terminal coupled to the source output, a reference resistor having a first terminal coupled to a second terminal of the sensor resistor and a second terminal coupled to the integrator input, and a comparator having a first comparator input coupled to the integrator output.

A method determines at least one power contact resistance or at least one resistance value corresponding to the at least one power contact resistance between at least one pack power contact of a battery pack and at least one apparatus power contact of an electrically driven work apparatus or of a charging apparatus. The pack power contact and the apparatus power contact touch one another and are loaded with a power current. The battery pack and the work apparatus or the charging apparatus are electrically connected by a data communication line for transmitting a data communication signal. The method determines the power contact resistance or the resistance value by comparing a signal voltage variable of the data communication line and a power voltage variable of the at least one pack power contact or of the apparatus power contact with one another, wherein the signal voltage variable or the power voltage variable is dependent on a voltage drop caused by the power current and the at least one power contact resistance.

A method and an integrated circuit for limiting a switchable load current. The integrated circuit includes a main transistor, through which in the conductive state a load current flows for supplying a load and a mirror transistor, a gate terminal of the mirror transistor being electrically connected to a gate terminal of the main transistor and a source terminal of the mirror transistor being electrically connected to a source terminal of the main transistor. The integrated circuit further includes a coupling circuit, which is configured to track a source drain voltage of the mirror transistor as a function of the source drain voltage of the main transistor. A gate control circuit is further provided, which limits the load current through the main transistor on the basis of a drain current through the mirror transistor.

A method and an integrated circuit for limiting a switchable load current. The integrated circuit includes a main transistor, through which in the conductive state a load current flows for supplying a load and a mirror transistor, a gate terminal of the mirror transistor being electrically connected to a gate terminal of the main transistor and a source terminal of the mirror transistor being electrically connected to a source terminal of the main transistor. The integrated circuit further includes a coupling circuit, which is configured to track a source drain voltage of the mirror transistor as a function of the source drain voltage of the main transistor. A gate control circuit is further provided, which limits the load current through the main transistor on the basis of a drain current through the mirror transistor.

In a meter for performing a measurement of an electrical parameter, an output from a sensor is sampled to produce at least one sample, and an iterative method is performed comprising: producing further samples; holding in memory a stored array of samples comprising the at least one sample and each of the further samples from each iteration; determining a measure of statistical variability of a mean for the respective iteration from a measure of statistical variability and from the number of samples used to generate the measure of statistical variability; comparing the measure of statistical variability of the mean with a pre-determined threshold; and generating an electrical signal indicating a state of the measurement if the measure of statistical variability of the mean of the samples taken during the measurement is less than or equal to the pre-determined threshold.