An object is to provide a semiconductor device that implements cost reduction as well as determination of withstand voltage characteristics. A semiconductor substrate includes a semiconductor element on the front surface thereof and a back surface electrode on the back surface thereof that controls the operation of the semiconductor element. A first electrode and a second electrode are provided in a terminal region outside an active region in which the semiconductor element is formed. An insulating film is provided between the first electrode and the second electrode. The second electrode is provided on an insulating interlayer film provided on the front surface of the semiconductor substrate. The first electrode is in contact with the front surface of the semiconductor substrate and is provided on the semiconductor substrate closer to an end portion thereof than the second electrode is, and is electrically connected to the back surface electrode.

A power system including a gate driver configured with test circuitry to detect faults is disclosed. The power system may be configured to test the fault detection circuitry in order to confirm its ability to detect faults. Various methods and circuit implementations are disclosed to determine the ability of the system to detect faults. The testing may include different configurations and protocols in order to make conclusions about which components are likely responsible for a failure. These components may include components included in the gate driver or externally coupled to the gate driver. The disclose approach does not significantly add complexity because a test input to initiate a test may be communicated from a low voltage side to a high voltage side over a shared communication channel.

A circuit for detecting faults affecting a power transistor comprises a conditioning circuit, a first fault status circuit, and a fault signaling circuit. The power transistor is turned on and off by assertion and de-assertion, respectively, of an input signal. The conditioning circuit produces a conditioned gate voltage signal from a gate voltage of the power transistor. The first fault status circuit asserts a first fault indication when the conditioned gate voltage signal is greater than a first fault reference voltage during a first interval after the assertion of the input signal. The fault signaling circuit asserts a fault signal in response to the first fault indication being asserted, and de-asserting the fault signal in response to the input signal being de-asserted.

In an embodiment, a method for testing a functional integrity of a transistor component, the method includes causing a first change of a charge state of an internal capacitance between control terminals of the transistor component; determining a capacitance value of the internal capacitance based on the first change of the charge state; causing a second change of the charge state of the internal capacitance; and evaluating a resistance value of an internal resistance between the control terminals based on the determined capacitance value and the second change of the charge state.

A method and system for predicting an insulated gate bipolar transistor (IGBT) lifetime based on compound failure mode coupling are provided. First, a simultaneous failure probability model of a bonding wire and a solder layer is calculated. Next, expectancy of the simultaneous failure probability model is calculated and recorded as a lifetime under a coupling effect. A coupling function relation is established. A lifetime of the solder layer and a lifetime of the bonding wire are predicted. An IGBT lifetime prediction model not taking the coupling effect into account is established. An IGBT lifetime prediction model taking the coupling effect into account is established. In the disclosure, the lifetime of the IGBT module under the coupling effect of the solder layer and the bonding wire may be accurately predicted.

In this testing device, a space in which a transistor 117 is disposed and a space in which a driving circuit for testing is disposed are separated by a partition wall 214. The driving circuit has a plurality of switch circuit boards 201, and a conductive plate 204 for connection is attached to the switch circuit board 201. A fork plug 205e is connected to a collector c terminal of the transistor 117 to be tested, and a fork plug 205c is connected to an emitter e terminal. The insertion of the fork plug 205 into an opening 216 provided in the partition wall 214 allows the connection of the fork plug 205 and the conductive plate 204. By changing the position of the opening 216 for inserting the fork plug 205, the connection to the driving circuit can be changed in accordance with an item to be tested.

Provided is an analyzing apparatus including a charge amount analyzing unit configured to analyze, by using a device simulator configured to simulate a transient change of a charge in a semiconductor device having a first main terminal and a second main terminal, a change of a charge amount at any one of the terminals when a power source voltage applied between the first main terminal and the second main terminal is changed by a displacement voltage smaller than an initial voltage after a current flowing between the first main terminal and the second main terminal is stabilized with the semiconductor device being set to an ON state and the power source voltage being set to the initial voltage, and a capacitance calculating unit configured to compute a terminal capacitance at any one of the terminals based on the change of the charge amount analyzed by the charge amount analyzing unit.

A semiconductor device in which a transistor has the characteristic of low off-state current is provided. The transistor comprises an oxide semiconductor layer having a channel region whose channel width is smaller than 70 nm. A temporal change in off-state current of the transistor over time can be represented by Formula (a2). In Formula (a2), I.sub.OFF represents the off-state current, t represents time during which the transistor is off, α and τ are constants, β is a constant that satisfies 0<β≤1, and C.sub.S is a constant that represents load capacitance of a source or a drain. $\begin{array}{cc}{I}_{\mathrm{OFF}}\left(t\right)=C_S\times \frac{\alpha \times \beta }{{\tau }^{\beta }}\times t^{\beta -1}\times e^{-{\left(\frac{t}{\tau }\right)}^{\beta }}& \left(\mathrm{a2}\right)\end{array}$

Provided is an analyzing apparatus including a charge amount analyzing unit configured to analyze, by using a device simulator configured to simulate a transient change of a charge in a semiconductor device having a first main terminal and a second main terminal, a change of a charge amount at any one of the terminals when a power source voltage applied between the first main terminal and the second main terminal is changed by a displacement voltage smaller than an initial voltage after a current flowing between the first main terminal and the second main terminal is stabilized with the semiconductor device being set to an ON state and the power source voltage being set to the initial voltage, and a capacitance calculating unit configured to compute a terminal capacitance at any one of the terminals based on the change of the charge amount analyzed by the charge amount analyzing unit.

A method for monitoring an online state of a bonding wire of an Insulated Gate Bipolar Translator (IGBT) module comprises the following steps: Step 1, constructing a full bridge inverter circuit and an online measuring circuit and connecting two input ends of the online measuring circuit to a collecting electrode and an emitting electrode of an IGBT power module of the full bridge inverter circuit to realize a connection of the full bridge inverter circuit and the online measuring circuit; Step 2, establishing a three-dimensional data model of a healthy IGBT; Step 3, establishing a three-dimensional data model of the IGBT with a broken bonding wire; Step 4, optimizing a least squares support vector machine by adopting a genetic algorithm; and Step 5, estimating states of the three-dimensional data models obtained in the Step 2 and the Step 3 by utilizing the optimized least squares support vector machine.