A serial IGBT voltage equalization method and system based on an auxiliary voltage source is disclosed. The method includes the following steps. (1) Detect a port dynamic voltage of each serial IGBT. (2) Perform dynamic overvoltage diagnosis respectively on the port dynamic voltage of each IGBT. (3) Supply emergency high level signal to the gate of the IGBT when there is dynamic overvoltage. (4) Stop supplying emergency high level signal to the gate of the IGBT, supply a constant voltage at the gate of the IGBT through the auxiliary voltage source. The invention provides a constant voltage through the auxiliary voltage source, prolongs the off time of the faulty IGBT, and turns off other IGBTs simultaneously, thereby achieving the purpose of serial IGBT voltage equalization.

A safety container for high-power, electronic device testing, the safety container including a first shell and first and second ports in the first shell. The first shell is configured to substantially surround a testing chamber sized to accommodate a device-under-test (DUT). The first shell is substantially rigid. The first port is configured to allow a fluid into the testing chamber, the second port configured to allow the fluid to exit the testing chamber.

The present application relates to the technical field of electronic circuits, and provides a gate detection circuit of an insulated gate bipolar transistor. The pulse shaping circuit is configured for shaping an input signal of a signal input device, and outputting a first square wave signal of a high level and a second square wave signal of a low level when the input signal is at the high level; and outputting a first square wave signal of the low level and a second square wave signal of the high level when the input signal is at the low level; the comparison circuit is configured for: comparing a first preset voltage with a voltage of a gate of the insulated gate bipolar transistor when the first square wave signal is at the high level, and outputting a low level when the first preset voltage is greater than the voltage of the gate of the insulated gate bipolar transistor; and comparing a second preset voltage with a voltage of a gate of the insulated gate bipolar transistor when the second square wave signal is at the high level, and outputting a low level when the second preset voltage is lower than the voltage of the gate of the insulated gate bipolar transistor; and the fault output circuit is configured for outputting a gate fault signal when the comparison circuit outputs the low level. The present application can detect the gate fault of the insulated gate bipolar transistor.

Provided is a test method comprising: preparing a plurality of groups for setting, each of which has a plurality of semiconductor devices for setting, and assigning an inspection voltage to each of the respective plurality of groups for setting; performing first testing by applying the assigned inspection voltage to the semiconductor devices for setting, and testing, at a first temperature, the plurality of semiconductor devices for setting included in each of the plurality of groups for setting; performing second testing by testing, at a second temperature different from the first temperature, a semiconductor device for setting having been determined as being non-defective and by detecting a breakdown voltage at which the semiconductor device for setting is broken; acquiring a relationship between the inspection voltage and the breakdown voltage; and setting an applied voltage used when testing a semiconductor device under test at the first temperature, based on the acquired relationship.

A semiconductor test apparatus according to the present disclosure includes: a stage on which a wafer is to be mounted; a pressurizing wall disposed on a surface of a probe card opposing the stage, extending toward the stage, and having an opening; a mark disposed on a lower surface of the pressurizing wall opposing the stage; a probe disposed in the opening; an air tube to force air into the opening; a detector to detect first spacing between a tip of the probe and the mark; and a controller to control second spacing between the wafer and the lower surface of the pressurizing wall based on the first spacing, wherein, when an electrical property of each of chips of the wafer is measured, the second spacing is controlled to be predetermined spacing by the controller, and the air is forced into the opening through the air tube.

A semiconductor module including a semiconductor element which is bonded to a wiring pattern part and connects or disconnects two main electrode terminals to or from each other according to a drive signal applied to a gate electrode terminal, includes a deterioration detecting circuit configured to use one main electrode terminal of the two main electrode terminals of the semiconductor element with an applied DC voltage, as a reference potential, and detect deterioration of a joining part of the semiconductor element on the basis of a gate voltage which is the voltage between the one main electrode terminal and the gate electrode terminal and an inter-main-electrode voltage which is the voltage between the one main electrode terminal and the other main electrode terminal, and outputs an alarm signal.

An assembly including an insulated gate bipolar transistor (IGBT) is provided. The IGBT is coupled with a gate driver for receiving a gating signal to drive the IGBT and providing a feedback signal of the IGBT which indicates a change of a collector-emitter voltage of the IGBT. The assembly further includes a failure mode detection unit for determining whether the IGBT is faulted based on a timing sequence of the gating signal and feedback signal. The failure mode detection unit is capable of differentiating fault types including a gate driver fault, a failed turn-on fault, a short-circuit fault, a turn-on over-voltage fault and a turn-off over-voltage fault. Accordingly, an IGBT failure mode detection method is also provided.

A semiconductor test apparatus according to the present disclosure includes: a stage on which a wafer is to be mounted; a pressurizing wall disposed on a surface of a probe card opposing the stage, extending toward the stage, and having an opening; a mark disposed on a lower surface of the pressurizing wall opposing the stage; a probe disposed in the opening; an air tube to force air into the opening; a detector to detect first spacing between a tip of the probe and the mark; and a controller to control second spacing between the wafer and the lower surface of the pressurizing wall based on the first spacing, wherein, when an electrical property of each of chips of the wafer is measured, the second spacing is controlled to be predetermined spacing by the controller, and the air is forced into the opening through the air tube.

The disclosure discloses an IGBT module reliability evaluation method and device based on bonding wire degradation, which belong to the field of IGBT reliability evaluation. The realization of the method includes: obtaining a relationship between a IGBT chip conduction voltage drop U.sub.ces and an operating current I.sub.c along with a chip junction temperature T.sub.c; for an IGBT module under test, obtaining the conduction voltage drop U.sub.ces-c of the IGBT chip through the operating current I.sub.c and the chip junction temperature T.sub.c; obtaining an external conduction voltage drop U.sub.ces-m of the IGBT module by using a voltmeter; performing subtraction to obtain a voltage drop at a junction of a IGBT chip and a bonding wire, and combining the operating current to obtain a resistance at the junction; determining that the IGBT module has failed when the resistance at the junction increases to 5% of an equivalent impedance of the IGBT module.

A semiconductor module including a semiconductor element which is bonded to a wiring pattern part and connects or disconnects two main electrode terminals to or from each other according to a drive signal applied to a gate electrode terminal, includes a deterioration detecting circuit configured to use one main electrode terminal of the two main electrode terminals of the semiconductor element with an applied DC voltage, as a reference potential, and detect deterioration of a joining part of the semiconductor element on the basis of a gate voltage which is the voltage between the one main electrode terminal and the gate electrode terminal and an inter-main-electrode voltage which is the voltage between the one main electrode terminal and the other main electrode terminal, and outputs an alarm signal.