A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.

A method for monitoring an ideal diode comprises controlling a source-gate voltage of a MOSFET of the ideal diode such that the ideal diode can be changed between an off and an on state with a first target value for a source-drain voltage. To detect error states, the source-drain voltage and the source-gate voltage are measured. A check is carried out to determine whether the source-drain voltage reaches the first target value within predefined error limits in the on state. A test mode is carried out, in which a second target value which smaller than the first target value is set for the source-drain voltage. A check is carried out to determine whether the source-gate voltage reaches an upper threshold value when the test mode is being carried out. An error signal is output when the first target value and/or the upper threshold value is/are not reached.

A test structure for a buried gate transistor includes a substrate, a first test contact located on one side of a first transistor contact, a second test contact located on one side of a second transistor contact, and a layer buried in the substrate, having a doping greater than or equal to 10.sup.18 cm.sup.−3, and having a face which is tangent to the buried part of the gate. A first insulation structure is disposed between the first test contact and the first transistor contact and a second insulation structure is disposed between the second test contact and the second transistor contact. The first and second test contacts each have an end connected to the buried layer.

A test and measurement circuit including a capacitor in parallel with a device under test, a direct current voltage source configured to charge the capacitor, a pulse generator configured to generate a pulse for testing the device under test, and a sensor for determining a current in the device under test.

Disclosed are method and an apparatus for analysis of an interface state of a MIS-HEMT device. By means of establishing an equivalent model of MIS-HEMT(s) that includes equivalent circuits representing a dielectric layer, a barrier layer and a channel layer, plotting a group of a capacitance-frequency function curve and a conductance-frequency function curve that can be best fitted to the measured capacitance-frequency scatter diagram and the measured conductance-frequency scatter diagram via the equivalent model, taking such best-fitted group as the fitted function curve group, and calculating parameters about the interface state of MIS-HEMT(s) according to the group of assigned values corresponding to the fitted function curve group, the parameters of the analyzed interface state can be more accurate since the fitted frequency function curve group can, with the aid of the equivalent model, simultaneously fit the measured capacitance-frequency scatter diagram and the measured conductance-frequency scatter diagram.

A system and method for performing in-situ measurements of semiconductor devices during chemical vapor deposition (CVD) includes disposing a chip carrier within a sealed chamber of a reactor for carrying out in-situ monitoring of partially fabricated semiconductor devices. The chip carrier includes a plurality of metallized bonding pads disposed along both peripheral edges on a same surface of the base for making electrical connections to metallized pads or contacts on the semiconductor device through bonding wires. Each of the plurality of metallized bonding pads disposed along both peripheral edges is electrically connected to each other as a pair through electrically connecting to a corresponding pair of ports which are disposed along both peripheral edges of the chip carrier. In-situ monitoring of the partially fabricated semiconductor device is performed through connecting the plurality of ports on the chip carrier to an external source-measure unit through a connector and wire harness.

A semiconductor test structure includes a field-effect transistor and a metal connection structure. The field-effect transistor includes a substrate with first doping type, a gate located on a surface of the substrate, and a source region with a second doping type and a drain region with the second doping type in the substrate, the source region and the drain region are located on two sides of the gate, respectively. The metal connection structure is connected with the gate; the metal connection structure forms a Schottky contact with the substrate.

A power supply control apparatus detects a failure of a semiconductor switch element in a switching circuit having semiconductor series circuits each having semiconductor switch elements connected in series with reverse polarities. The power supply control apparatus includes a reference resistance value storing unit storing information on a combined resistance value between an input and an output of the switching circuit, a conduction current detection unit configured to detect a current flowing through the switching circuit, a potential difference detection unit configured to detect an input-output potential difference between the input and the output of the switching circuit, a voltage drop calculation unit configured to calculate an assumed voltage drop, a voltage comparison unit configured to compare the input-output potential difference with the assumed voltage drop, and a failure identification unit configured to identify a failure of the semiconductor switch element.

A system to monitor a MOSFET, the system including a switching arrangement configured to switchably isolate a gate terminal of the MOSFET and a source terminal of the MOSFET from a gate-control voltage source and a test circuit configured to detect a change in a gate-to-source voltage of the MOSFET over a test period, the test period occurring while the gate terminal and the source terminal are isolated

A body diode is energized by inputting a BD energization pulse signal having a predetermined cycle. At the start of energization of the body diode and immediately before termination thereof, an ON signal of a Von measurement pulse signal is input to a high-temperature semiconductor chip at a timing different from that of an ON signal of the BD energization pulse signal, thereby passing a drain-source current through a MOSFET, and a drain-source voltage is measured. Thereafter, energization of the body diode is terminated. At room temperature before and after the energization of the body diode, the drain-source voltage is measured by inputting the ON signal of the Von measurement pulse signal. A semiconductor chip for which a fluctuation amount of the drain-source voltage at a high temperature and a fluctuation amount of the drain-source voltage at room temperature are within predetermined ranges is determined to be a conforming product.