A monitoring circuit according to an embodiment of the present disclosure includes a booster configured to amplify a current amount between a terminal to which a power voltage is applied and a ground terminal to generate a sensing voltage, and an oscillator configured to output a sensing signal of which a frequency is adjusted in response to the sensing voltage, wherein the booster includes a transistor having a first size and a transistor having a second size greater than the first size, and wherein the oscillator includes a plurality of transistors having a third size greater than the first size.

Provided is a method of determining a gate capacitance of a semiconductor device having a source, a drain, a gate, and a channel, the semiconductor device being arranged in a circuit further comprising an electrical resonator, wherein one of the source, the drain, and the gate is connected to the electrical resonator. The method comprises: measuring a resonance frequency of the circuit; and calculating, based on the resonance frequency, the gate capacitance. Since it is not necessary to pass a current through the semiconductor device, an accurate measurement of gate capacitance may be achieved. Also provided are an apparatus for determining a gate capacitance, a probe for measuring gate capacitance, and a related computer program product.

A semiconductor device includes a first test structure including a first portion of a conductive structure and a second portion of the conductive structure located within a first lateral wiring layer of a layer stack of the semiconductor device. The first portion of the conductive structure of the first test structure is electrically connected to the second portion of the conductive structure of the first test structure through a third portion located within a second lateral wiring layer of the layer stack arranged above the first lateral wiring layer. Further, the first portion of the conductive structure of the first test structure is electrically connected to a gate of a test transistor structure, a doping region of the test transistor structure or an electrode of a test capacitor. Additionally, the first portion of the conductive structure of the first test structure is electrically connected to a first test pad of the first test structure.

An example semiconductor wafer includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, and a layer of the metal disposed on the dielectric layer. An example method of determining an effective work function of a metal on the semiconductor wafer includes determining a surface barrier voltage of the semiconductor wafer, and determining a metal effective work function of the semiconductor wafer based, at least in part, on the surface barrier voltage.

A compact millimeter-wave slide screw impedance tuner allows reducing to a minimum the insertion loss between the tuner and the wafer-probe. The structure of the tuner uses a 1 mm slabline and adapters, an eccentrically rotating remotely controlled wideband tuning probe and a sliding rack on which the tuning-probe is attached; the position of the rack is controlled by a permanently anchored motorized pinion. The construction method allows for maximum compactness, needed in order to be able to attach the tuner directly on the wafer-probe and minimize the insertion loss, while maintaining key advantages of electro-mechanical tuners, such as robustness, linearity, simplicity, tuning resolution and calibration and compatibility with existing load pull software and technology.

A monitoring circuit according to an embodiment of the present disclosure includes a booster configured to amplify a current amount between a terminal to which a power voltage is applied and a ground terminal to generate a sensing voltage, and an oscillator configured to output a sensing signal of which a frequency is adjusted in response to the sensing voltage, wherein the booster includes a transistor having a first size and a transistor having a second size greater than the first size, and wherein the oscillator includes a plurality of transistors having a third size greater than the first size.

Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (f.sub.T) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (V.sub.d1); extracting a transconductance (G.sub.m) from the first set of in-line DC parameters as a function of a gate-voltage (V.sub.g) and the first drain-voltage (V.sub.d1); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (V.sub.d2); extracting a total gate capacitance (C.sub.gg) from the second set of in-line DC parameters as a function of the gate-voltage (V.sub.g); and predicting the unity gain frequency (f.sub.T) of the MOSFET based upon the extracted transconductance (G.sub.m) and the extracted total gate capacitance (C.sub.gg).

A semiconductor device includes a first test structure including a first portion of a conductive structure and a second portion of the conductive structure located within a first lateral wiring layer of a layer stack of the semiconductor device. The first portion of the conductive structure of the first test structure is electrically connected to the second portion of the conductive structure of the first test structure through a third portion located within a second lateral wiring layer of the layer stack arranged above the first lateral wiring layer. Further, the first portion of the conductive structure of the first test structure is electrically connected to a gate of a test transistor structure, a doping region of the test transistor structure or an electrode of a test capacitor. Additionally, the first portion of the conductive structure of the first test structure is electrically connected to a first test pad of the first test structure.

Provided is a semiconductor device including a MOS analog circuit which has a high reliability and a low manufacturing cost, and in which latent failure is easily detected. The MOS analog circuit is switched to a test state or an operating state based on a control signal that is externally supplied. In the test state, a voltage between a power supply terminal and a reference terminal is applied to a gate oxide film of a MOS transistor included in the MOS analog circuit.

Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (f.sub.T) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (V.sub.d1); extracting a transconductance (G.sub.m) from the first set of in-line DC parameters as a function of a gate-voltage (V.sub.g) and the first drain-voltage (V.sub.d1); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (V.sub.d2); extracting a total gate capacitance (C.sub.gg) from the second set of in-line DC parameters as a function of the gate-voltage (V.sub.g); and predicting the unity gain frequency (f.sub.T) of the MOSFET based upon the extracted transconductance (G.sub.m) and the extracted total gate capacitance (C.sub.gg).