The present disclosure relates to a method for estimating parameters of a junction of a power semi-conductor element comprising: •—Detecting at least one stable on-line operating condition through measurements (2, 3, 4) of Von, Ion, Tc on a semi-conductor module (1) where Ion is a current for which the on-state voltage Von of the semi-conductor is sensitive to the temperature and Tc is the temperature of the casing of said semi-conductor element; •—Measuring and storing at least one parameter set Von, Ion, Tc of said at least one stable operating condition; •—in a calculating unit (52), providing calculations for minimizing the error between a junction temperature estimation Tj of an electrical model Tj=F(Von, Ion, θelec) comprising a first set of unknown parameters θelec and another junction temperature estimation Tjmod of a loss/thermal model Tj=G(lon, Tc, θ mod) comprising a second set of unknown parameters θ mod and obtaining at least one set of parameters θelec and at least one parameter θ mod providing minimization of said error; •—providing the calculated value of Tj with at least one of the calculated parameters sets θelec and/or θ mod and the measured Von, Ion, Tc; •—Storing the at least one parameters set θelec and/or θ mod and/or Tj.

A contact resistance test method and related devices are provided. When a MOS transistor working in a linear region is tested, a functional relationship between the channel width of the MOS transistor and total resistances of the MOS transistor at sampling temperatures is determined, to determine the contact resistance of the MOS transistor at the sampling temperatures. A calibration coefficient of the contact resistance at a current ambient temperature is determined based on the contact resistance of the MOS transistor at the sampling temperatures. A measurement result of the contact resistance is further adjusted based on the calibration coefficient of the contact resistance at the current ambient temperature, to obtain an accurate contact resistance at the current ambient temperature.

The present disclosure provides techniques for predicting failure of power switches and taking action based on the predictions. In an example, a method can include controlling the at least two parallel-connected power switches via a first driver and a second driver, the first a second driver responsive to a single command signal, measuring a failure characteristic of a first power switch, and disabling a first driver of the first power switch when the first failure characteristic exceeds a failure precursor threshold.

A power supply circuit for measuring transient thermal resistances includes an inverter circuit provided on a primary side of a transformer and controlled by a PWM signal, a rectifier circuit provided on a secondary side of the transformer and including a DC reactor, and a control circuit controlling the PWM signal so as to output a pulsed output current from the rectifier circuit to a semiconductor device to be measured. The control circuit sets a first PWM frequency at rising timing of the output current, and sets a second PWM frequency when a predetermined time t1 elapses from the rising timing of the output current. The control circuit sets the first PWM frequency higher than the second PWM frequency.

The present invention provides a system and method for measuring intermittent operating life (IOL) of a GaN-based device under test (DUT) is provided. The system is operable in a stressing mode, a cooling mode and a measure mode. A power regulation approach is adopted to ensure that DUT of the same thermal resistance have same temperature increase during the IOL test. The present invention eliminates the influence caused by parasitic parameters of testing circuits and the inconsistency of threshold voltage and drain-source resistance of the device itself. Through power regulation, it is the junction temperature of the device, not the housing temperature of the device, being directly controlled. Therefore, higher measurement accuracy can be achieved.

A contact resistance test method and related devices are provided. When a MOS transistor working in a linear region is tested, a functional relationship between the channel width of the MOS transistor and total resistances of the MOS transistor at sampling temperatures is determined, to determine the contact resistance of the MOS transistor at the sampling temperatures. A calibration coefficient of the contact resistance at a current ambient temperature is determined based on the contact resistance of the MOS transistor at the sampling temperatures. A measurement result of the contact resistance is further adjusted based on the calibration coefficient of the contact resistance at the current ambient temperature, to obtain an accurate contact resistance at the current ambient temperature.

A sensor system included in an integrated circuit includes multiple sensor circuits and a control circuit. Using characterization data, a model may be generated that defines a relationship between measurable parameters of the integrated circuit and an operating characteristic of the integrated circuit. The control circuit can combine, using a function included in the model, data from the multiple sensor circuits to determine a value of the operating characteristic that is more accurate than a sensor circuit configured to measure a single parameter of the integrated circuit that varies with the operating characteristic.

A method analyzes an operation of a power semiconductor device. The method includes: providing a set of reference voltages of the device and a set of corresponding reference currents; measuring, within a predetermined time-interval, Nframe on-state voltages and Nframe corresponding on-state currents of the device to obtain Nframe measurement points, Nframe being an integer number equal to or greater than 2; adapting the set of reference voltages by carrying out a least squares fit to the Nframe measurement points; and using the adapted set of reference voltages to analyze the operation of the power semiconductor device.

A drive device for driving a voltage-controlled semiconductor element. The drive device includes: a drive circuit connected to the gate of the semiconductor element via a gate resistor; a delay circuit connected to the drive circuit, for delaying a drive signal output from the drive circuit until a gate voltage of the semiconductor element enters a Miller effect period, which is a period during which the gate voltage transitionally changes, the gate voltage having temperature dependency on a chip temperature of the semiconductor element; a one-shot circuit connected to the delay circuit, for outputting a pulse signal with a pulse width shorter than the Miller effect period; a comparator that compares the gate voltage with a reference voltage; and an AND circuit that outputs an overheat detection signal in response to the gate voltage exceeding the reference voltage.

A design-for-test circuit for evaluating a BTI effect is disclosed, the DFT circuit comprises a plurality of stress generators having logic circuits with a plurality of input and output terminals. Each output terminal is connected to the grid of the device to be tested. In a stress mode, a stress input signal is selected from a frequency signal, a first direct current voltage, and a second direct current voltage, all stress output signals formed by all the stress generators comprise the first direct current voltage, a series of frequency signals with different duty cycles, and the second direct current voltage, and all the stress output signals are used in combination such that the stress times regarding the device under test within the same test time have a plurality of different values, so as to evaluate the BTI effect of the device under test having different values of the stress times.