A method for fabricating a MOMCAP includes steps as follows: An Nth metal layer is formed on a substrate according to an Nth expected capacitance value of the Nth metal layer. An Nth capacitance error value between an Nth actual capacitance value of the Nth metal layer and the Nth expected capacitance value is calculated. An N+1th expected capacitance value of an N+1th metal layer is adjusted to form an N+1th actual capacitance value according to the Nth capacitance error value, and the N+1th metal layer with an N+1th actual capacitance value is formed on the Nth metal layer according to the adjusted N+1th expected capacitance value, to make the sum of the Nth actual capacitance value and the N+1th actual capacitance value equal to the sum of the Nth expected capacitance value and the N+1th expected capacitance value. N is an integer greater than 1.

In an approach utilizing static analysis, a processor receives a netlist for an integrated circuit. For at least one node of the integrated circuit in the netlist, a processor calculates (i) a total capacitive load of the respective node and (ii) a minimum required driver size. For a driver of the respective node, a processor (i) determines an effective driver size of the driver based on at least a number of fins of the driver and (ii) determines that the effective driver size exceeds the minimum required driver size multiplied by a predefined sizing margin. A processor, responsive to determining that the effective driver size exceeds the minimum required driver size multiplied by the predefined sizing margin, generates a report, where the report includes at least the driver and a suggestion to reduce the effective size of the driver.

A system to detect gate-open failures in a MOS based insulated gate transistor can include a detection circuit, including a first circuit configured to measure a drain-source voltage across the MOS based insulated gate transistor, a first comparator circuit can be configured to compare the measured drain-source voltage to a threshold drain-source conduction voltage indicating a conduction state of a channel of the MOS based insulated gate transistor, a second circuit can be configured to measure a gate voltage applied at a gate of the MOS-based insulated gate transistor, a second comparator circuit can be configured to compare the gate voltage applied at the gate to a threshold gate voltage for the MOS based insulated gate transistor to provide an indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel and a logic circuit can be configured to detect a gate-open failure of the MOS based insulated gate transistor based on the conduction state of the channel and the indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel when the MOS based insulated gate transistor is in an on state or an off state.

A high-frequency 5 measurement method includes generating a test signal (TS), which is a sine-wave signal having a predetermined frequency, in which a period (τ) during which the power level is at a first power level and a period (T-τ) during which the power level is at a second power level lower than the first power level 10 are periodically repeated, inputting the test signal (TS) to a device under test (10) as an input signal, and measuring the difference between an output signal (OUT) of the device under test (10) and an ideal value of the output signal (OUT).

A system to detect gate-open failures in a MOS based insulated gate transistor can include a detection circuit, including a first circuit configured to measure a drain-source voltage across the MOS based insulated gate transistor, a first comparator circuit can be configured to compare the measured drain-source voltage to a threshold drain-source conduction voltage indicating a conduction state of a channel of the MOS based insulated gate transistor, a second circuit can be configured to measure a gate voltage applied at a gate of the MOS-based insulated gate transistor, a second comparator circuit can be configured to compare the gate voltage applied at the gate to a threshold gate voltage for the MOS based insulated gate transistor to provide an indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel and a logic circuit can be configured to detect a gate-open failure of the MOS based insulated gate transistor based on the conduction state of the channel and the indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel when the MOS based insulated gate transistor is in an on state or an off state.

Hardware test systems are provided that have an electrical test loop with a minimum length of less than 200 mm, a maximum di/dt capacity of at least 1500 A/μs and a minimum parasitic inductance of less than 100 nH. The hardware tests systems can be used for commutation measurement or other test applications requiring low stray inductance.

An apparatus includes a resistor and a circuit. The resistor may be fabricated on a die using a semiconductor process. The circuit may be fabricated on the die using the semiconductor process and may be configured to (i) generate a measurement voltage at a node of the resistor as a function of a capacitance value and a frequency of a clock signal and (ii) generate a codeword in response to the measurement voltage. The codeword generally has a plurality of possible values. A particular value of the possible values may verify that the voltage is between a plurality of threshold voltages.

In an approach utilizing static analysis, a processor receives a netlist for an integrated circuit. For at least one node of the integrated circuit in the netlist, a processor calculates (i) a total capacitive load of the respective node and (ii) a minimum required driver size. For a driver of the respective node, a processor (i) determines an effective driver size of the driver based on at least a number of fins of the driver and (ii) determines that the effective driver size exceeds the minimum required driver size multiplied by a predefined sizing margin. A processor, responsive to determining that the effective driver size exceeds the minimum required driver size multiplied by the predefined sizing margin, generates a report, where the report includes at least the driver and a suggestion to reduce the effective size of the driver.

A test circuit includes a pull-up device, a pull-down device, a switch circuit and a voltage-setting unit. The pull-up device is used to receive a first control signal and coupled to a first end of the device-under-test. The pull-down device is used to receive a second control signal and coupled to the first end of the device-under-test. The switch unit is controlled by a switch signal, used to receive a testing signal and coupled to a second end of the device-under-test. The voltage-setting unit is controlled by a third control signal, used to pull the second end of the device-under-test to a predetermined voltage.

Systems, devices, and methods for characterizing semiconductor devices and thin film materials. The device consists of multiple probe tips that are integrated on a single substrate. The layout of the probe tips could be designed to match specific patterns on a CMOS chip or sample. The device provides for detailed studies of transport mechanisms in thin film materials and semiconductor devices.