An exemplary method of detecting a Trojan circuit in an integrated circuit is related to applying a test pattern comprising an initial test pattern followed by a corresponding succeeding test pattern to a golden design of the integrated circuit, wherein a change in the test pattern increases side-channel sensitivity; measuring a side-channel parameter in the golden design of the integrated circuit after application of the test pattern; applying the test pattern to a design of the integrated circuit under test; measuring the side-channel parameter in the design of the integrated circuit under test after application of the test pattern; and determining a Trojan circuit to be present in the integrated circuit under test when the measured side-channel parameters vary by a threshold.

A system and method are disclosed for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.

A method and a system for fault verification of an electronic device are provided. The electronic device includes a device to-be-verified. The method includes the following. A first power-supply voltage is applied to the electronic device until the device to-be-verified satisfies a material-failure condition. A second power-supply voltage is applied to the electronic device to determine whether the electronic device has safety risk. The first power-supply voltage is higher than the second power-supply voltage, and the safety risk is caused by material failure in the device to-be-verified. The method and the system for fault verification of an electronic device can verify safety risk caused by material failure in internal components of the electronic device.

A power supply is configured to perform an at least partial compensation of a voltage variation caused by a load change using a voltage variation compensation mechanism which is triggered in response to an expected load change. An Automated test equipment for testing a device under test comprises a power supply, which is configured to supply the device under test. The automated test equipment comprises a pattern generator configured to provide one or more stimulus signals for the device under test. The power supply is configured to perform an at least partial compensation of a voltage variation caused by a load change using a voltage variation compensation mechanism which is activated in synchronism with one or more of the stimulus signals and/or in response to one or more response data signals from the device under test. Corresponding methods and a computer program are also described.

A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.

An apparatus for testing a transducer module includes a test signal generator coupled to a common-mode terminal common to a plurality of transducers, and a signal processing circuit configured to receive output signal from each of said transducers and to produce an output signal. If the transducers are well matched to one another, the output signal will have little or no output amplitude. If there is a mismatch between the transducers, however, the output signal will have an amplitude proportional to the mismatch. The amplitude of the output signal may be compared to a predetermined threshold in order to produce a mismatch output signal indicating the existence of, and/or the degree of, mismatch between the transducers.

Methods, systems and techniques are provided to authenticate a device under test (DUT)/system under test (SUT) comprising an electronic component(s). A profile is defined by injecting a signal to elicit an output that is responsive a physical characteristic of the type of DUT/SUT. In respective embodiments the injected signal is defined to elicit an output for time-domain or frequency-domain evaluation. An injected signal may comprise combinations of (non-destructive/non-activating) signals applied to multiple access points for measurement at arbitrary access points of the DUT/SUT. In an embodiment, measurements of multiple DUT/SUTs of a same type are used to define a common profile. In an embodiment, the profile is built using machine learning to define a classifier. In other embodiments, statistical profiles are defined. During use, output is generated for a target DUT/SUT for evaluation relative to the profile. Counterfeit/alternate designs, altered designs, and implants are detectable.

The invention relates to a method and a device for identifying and locating cyclic momentary insulation faults in an ungrounded power supply system, the method comprising the steps: detecting a fault current caused by the momentary insulation fault as a differential current in the branch circuit to be monitored and displaying the temporal progression of the differential current via a differential current signal by means of a differential current sensor; providing a processing signal which temporally describes a process sequence of a process taking place in the consumer; correlating the differential current signal with the processing signal in a computing unit in order to yield a correlation signal as a measure for a temporal match between the differential current signal and the processing signal; signaling the momentary insulation fault via the computing unit by means of a signaling signal if the correlation signal shows the temporal match. The device according to the invention has a differential current sensor and a computing unit so that it can implement the method according to the invention.

The present disclosure a program burning device configured to read or write to a program burning interface. The program burning device includes a microprocessor, a programming drive circuit and an overcurrent protection circuit. The microprocessor outputs a first test signal or a second test signal. The programming drive circuit outputs a high driving voltage or a low driving voltage to the program burning interface. After the programming drive circuit outputs the low driving voltage for a preset time, the programming drive circuit outputs the high driving voltage to make the program burning interface form a high impedance. Afterwards, the overcurrent protection circuit receives the first test signal to trigger the overcurrent protection, and then receives the second test signal to trigger the undercurrent protection. If triggering the overcurrent protection and the undercurrent protection are continuously failed over a preset number of times, the microprocessor determines that current protection is failed.

An example test system includes a test head, and a device interface board (DIB) configured to connect to the test head. The DIB is for holding devices under test (DUTs). The DIB includes electrical conductors for transmitting electrical signals between the DUTs and the test head. Servers are programmed to function as test instruments. The servers are external to, and remote from, the test head and are configured to communicate signals over fiber optic cables with the test head. The signals include serial signals.