A method and a testing apparatus related to wafer testing are provided. In the method, testing raw data is obtained by a testing apparatus operating with a Unix-related system. The testing raw data is a testing result of probe testing on one or more wafers by the testing apparatus. The testing raw data is converted into converted data by the testing apparatus. The converted data is related to the defect information of the wafer. Analyzed data is generated by the testing apparatus according to the converted data. The analyzed data is used for a graphical interface. Therefore, real-time defect analysis during the testing procedure may be provided.

Provided is a semiconductor device that can detect the cracking progress with high precision. A semiconductor device is formed using a semiconductor substrate, and includes an active region in which a semiconductor element is formed, and an edge termination region outside the active region. A crack detection structure is termed in the edge termination region of the semiconductor substrate. The crack detection structure includes: a trench formed in the semiconductor substrate and extending in a circumferential direction of the edge termination region; an inner-wall insulating film formed on an inner wall of the trench; an embedded electrode formed on the inner-wall insulating film and embedded into the trench; and a monitor electrode formed on the semiconductor substrate and connected to the embedded electrode.

The present application relates to a test circuit, comprising: M stages of test units, first terminals of test units in each stage being all connected to a power wire, second terminals of test units in each stage being all connected to a ground wire, third terminals of test units in the first stage being connected to the power wire, and third terminals of test units in the i.sup.th stage being connected to fourth terminals of test units in the (i−1).sup.th stage; wherein, the M and i are positive integers greater than or equal to 2.

A design-for-test circuit for evaluating a BTI effect is disclosed, the DFT circuit comprises a plurality of stress generators having logic circuits with a plurality of input and output terminals. Each output terminal is connected to the grid of the device to be tested. In a stress mode, a stress input signal is selected from a frequency signal, a first direct current voltage, and a second direct current voltage, all stress output signals formed by all the stress generators comprise the first direct current voltage, a series of frequency signals with different duty cycles, and the second direct current voltage, and all the stress output signals are used in combination such that the stress times regarding the device under test within the same test time have a plurality of different values, so as to evaluate the BTI effect of the device under test having different values of the stress times.

A semiconductor structure includes: a through silicon via penetrating a base; and a protection structure, including: a conductive first test ring and a conductive second test ring both arranged around the through silicon via and electrically insulated from the through silicon via; a first dielectric layer located between the first test ring and the second test ring and configured to electrically isolate the first test ring from the second test ring; and a first connection layer located in the first dielectric layer and configured to be electrically connected to the first test ring and the second test ring.

A test circuit includes one or more sensors adapted to be formed on a wafer, each sensor detecting one or more wafer characterization data in a stressed condition; a stress generator controlling the one or more sensors to place the one or more sensors under stress during wafer manufacturing; memory coupled to the one or more sensors to store wafer characteristics under the stressed condition; and an interface coupled to the memory to communicate the wafer characterization data to a tester.

A timer circuit includes a plurality of n-type field effect transistors (NFETs) powered by a current source, a plurality of electromigration detection elements each electrically connected to a respective NFET of the plurality of NFETs, and a read-out circuit electrically connected to the plurality of electromigration detection elements to meter usage of each of the NFETs.

A system for electromigration testing is disclosed. The system includes a conductive member, a cap layer of insulative material over at least a portion of a top surface of the conductive member, a cathode conductively connected to a first end of the conductive member; an anode conductively connected to a second end of the conductive member, and a current source conductively connected to the cathode and the anode. A plurality of sensory pins are disposed along a length of the conductive member between the first end and the second end of the conductive member. The sensory pins are conductively connected to a bottom surface of the conductive member. At least one measurement device is conductively connected to at least one sensory pin of the plurality of sensory pins. The at least one measurement device determines a resistance of at least one portion of the conductive member.

Systems and methods for electrically testing electromigration in an electromigration test structure are disclosed herein. The systems include a voltage control portion, a current control portion, and a current regulating structure. The systems further include an electric current detector, a first system connection, and a second system connection. The systems also include a voltage detector, and a controller. In some embodiments of the methods, a voltage control portion regulates a high-side signal electric current to maintain a voltage difference below a voltage setpoint while a current control portion maintains the high-side signal electric current below a threshold current value. In some embodiments of the methods, one of the voltage difference and a magnitude of the high-side signal electric current is selected as a primary control parameter while the other is selected as a compliant control parameter.

An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.