Patent classifications
G01R31/2879
INTERFACE BOARD FOR TESTING IMAGE SENSOR, TEST SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF
A testing system for testing an image sensor, includes a probe card, a pogo block receiving output signals of the probe card, an interface board configured to receive output signals of the pogo block, convert the received output signals of the pogo block, and output the converted signals through a cable, and a testing apparatus connected to the interface board through the cable. The testing apparatus is configured to test the device under test through signals received through the cable. The interface board includes an active interface module configured to amplify the received output signals of the pogo block, convert the amplified signals into signals having a same frequency as the received output signals of the pogo block, and transmit the converted signals to the cable.
Test circuit and method
A test circuit includes an oscillator configured to generate an oscillation signal, a device-under-test (DUT) configured to output an AC signal based on the oscillation signal, a first detection circuit configured to generate a first DC voltage having a first value based on the oscillation signal, and a second detection circuit configured to generate a second DC voltage having a second value based on the AC signal.
System and method for testing radiation susceptibility capable of simulating impact of a radiation wave to a device under test
Abstract of Disclosure A method for testing radiation susceptibility includes transmitting radiation wave to a device under test, measuring the device under test to generate a first voltage according to the radiation wave, outputting a reference voltage to a coupling device so that the coupling device generates a second voltage according to the reference voltage, adjusting the reference voltage so that the second voltage approximates the first voltage, storing the adjusted reference voltage, outputting the second voltage to the device under test according to the adjusted reference voltage to simulate an impact of the radiation wave to the device under test, the device under test accordingly transmitting a control signal to the coupling device after receiving the second voltage, and determining a status of the device under test according to the control signal.
Functional test equipment including relay system and test method using the functional test equipment
The present disclosure provides functional test equipment for a device under test and method of testing the device under test. The functional test equipment includes a first power supply, a second power supply and a relay system. The first power supply is configured to generate a first supply voltage. The second power supply is configured to generate a second supply voltage different from the first supply voltage. The relay system is configured to electrically couple the first power supply or the second power supply to the device under test, wherein the first supply voltage is applied to the device under test for a first duration and the second supply voltage is applied to the device under test for a second duration less than the first duration.
Root monitoring on an FPGA using satellite ADCs
Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.
PHASE-INDEPENDENT TESTING OF A CONVERTER
A method and apparatus for performing an on-system built-in self-test of a converter are provided. In the method, a controller generates a test signal and outputs the test signal to the converter. The controller receives a response signal from the converter and determines a plurality of bin powers of a plurality of bins, respectively, of a frequency domain signal representative of the response signal. The controller determines a figure of merit for the converter based on a first bin power of a first bin of the plurality of bin powers, where the first bin corresponds to a frequency of the test signal.
FORM FACTOR EQUIVALENT LOAD TESTING DEVICE
An electronic load testing system is configured to emulate aspects of an integrated circuit (IC). A control module of the system is configured to be electrically coupled to a first location on a printed circuit board (PCB) of an electronic assembly, and a load module is configured to be electrically coupled to a second location on the PCB. The load module includes a load cell configured to selectively conduct current from a power supply of the electronic assembly. The first location and the second location are spaced apart and in electronic communication via one or more traces of the PCB. The control module is configured to communicate with the load module via the one or more traces of the PCB. In some examples, the load module and the IC have an equivalent form factor, such that the load module can be installed in place of the IC.
METHOD AND DEVICE FOR ADAPTING TEMPERATURES OF SEMICONDUCTOR COMPONENTS
A method and device for adapting temperatures of semiconductor components. The device includes a first and second semiconductor component, and an evaluation unit. The evaluation unit is configured to ascertain a first and second temperature of the first and second semiconductor component, respectively, calculate a first and second temperature deviation, which represents a deviation of the first and second temperature from a reference temperature, respectively, and adapt a first gate voltage of the first semiconductor component and/or a second gate voltage of the second semiconductor component until the first temperature deviation and the second temperature deviation are smaller than or equal to a predefined maximum allowable temperature deviation from the reference temperature. The adaptation takes place only when a predefined allowable control range for the respective gate voltage is not exceeded, and when the first temperature and/or the second temperature is/are greater than the reference temperature.
Electrical Device
In an embodiment a method includes providing a substrate having at least one conductor track situated thereon, applying at least one accumulation of an electrically conductive material to a surface of the conductor track, providing a carrier having at least one electrical contact, applying an electrically conductive adhesive to the at least one accumulation of the electrically conductive material and/or the at least one electrical contact and arranging the substrate and the carrier such that the accumulation of the electrically conductive material and the at least one electrical contact are situated opposite and at a distance from one another, wherein the electrically conductive adhesive forms a mechanical and electrical connection between the accumulation of the electrically conductive material and the at least one electrical contact, and wherein an interspace between the at least one accumulation of the electrically conductive material and the at least one electrical contact is filled with the electrically conductive adhesive.
APPARATUS AND METHOD FOR PROBING MULTIPLE TEST CIRCUITS IN WAFER SCRIBE LINES
An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. There are test circuit sites in the scribe lines, each test circuit site including contact pads for simultaneous connection to probe card needles, sensor circuit select and control circuitry, and a sensor circuit bank.