An integrated circuit with a switched signal path and circuitry configured to determine an anticipated specification current through the signal path.

A current measurement apparatus comprises: a capacitor connected in parallel to a signal terminal of a device under test (DUT); a test pattern generation apparatus generating a test pattern to operate the DUT; and a measurement module connected to one end of the capacitor. The measurement module comprises: an input/output (I/O) buffer increasing or reducing an amount of charges of the capacitor and outputting a signal corresponding to an output logic value according to a voltage of the one end of the capacitor; a time measurer measuring an arrival time which it takes for the voltage of the one end of the capacitor to reach a second voltage from a first voltage; and a controller controlling the i/o buffer and the time measurer to measure the arrival time and controlling such that a value of a current related to an inspection of a DUT is measured using the arrival time.

A sensor integrated circuit including a regulator for generating a regulated voltage includes a digital load configured to draw a load current from the regulator in response to a clock signal during in situ operation and a comparator configured to determine the absence or presence of a fault during in situ operation. The load current is less than or equal to a predetermined level in the absence of a fault and is greater than the predetermined level in the presence of a fault. The comparator is responsive to the load current and to a threshold level and is configured to generate a comparator output signal having a level indicative of whether the load current is less than or greater than the threshold level in order to thereby determine the absence or presence of a fault during in situ operation, respectively.

An integrated circuit with a switched signal path and circuitry configured to determine an anticipated specification current through the signal path.

A sensor integrated circuit including a regulator for generating a regulated voltage includes a digital load configured to draw a load current from the regulator in response to a clock signal during in situ operation and a comparator configured to determine the absence or presence of a fault during in situ operation. The load current is less than or equal to a predetermined level in the absence of a fault and is greater than the predetermined level in the presence of a fault. The comparator is responsive to the load current and to a threshold level and is configured to generate a comparator output signal having a level indicative of whether the load current is less than or greater than the threshold level in order to thereby determine the absence or presence of a fault during in situ operation, respectively.

A sensor integrated circuit including a regulator for generating a regulated voltage includes a digital load configured to draw a load current from the regulator in response to a clock signal during in situ operation and a comparator configured to determine the absence or presence of a fault during in situ operation. The load current is less than or equal to a predetermined level in the absence of a fault and is greater than the predetermined level in the presence of a fault. The comparator is responsive to the load current and to a threshold level and is configured to generate a comparator output signal having a level indicative of whether the load current is less than or greater than the threshold level in order to thereby determine the absence or presence of a fault during in situ operation, respectively.

A sensor integrated circuit including a regulator for generating a regulated voltage includes a digital load configured to draw a load current from the regulator in response to a clock signal during in situ operation and a comparator configured to determine the absence or presence of a fault during in situ operation. The load current is less than or equal to a predetermined level in the absence of a fault and is greater than the predetermined level in the presence of a fault. The comparator is responsive to the load current and to a threshold level and is configured to generate a comparator output signal having a level indicative of whether the load current is less than or greater than the threshold level in order to thereby determine the absence or presence of a fault during in situ operation, respectively.

A current measurement apparatus comprises: a capacitor connected in parallel to a signal terminal of a device under test (DUT); a test pattern generation apparatus generating a test pattern to operate the DUT; and a measurement module connected to one end of the capacitor. The measurement module comprises: an input/output (I/O) buffer increasing or reducing an amount of charges of the capacitor and outputting a signal corresponding to an output logic value according to a voltage of the one end of the capacitor; a time measurer measuring an arrival time which it takes for the voltage of the one end of the capacitor to reach a second voltage from a first voltage; and a controller controlling the i/o buffer and the time measurer to measure the arrival time and controlling such that a value of a current related to an inspection of a DUT is measured using the arrival time.

An apparatus and a method which use a programmable reliability aging timer are provided. The apparatus includes a performance circuit configured to perform a function of an integrated circuit (IC), a memory unit configured to store a lifetime of the IC, a controller configured to set an aging target condition according to the lifetime stored in the memory unit, and a reliability aging timer (RAT) configured to apply stress to a test pattern according to the aging target condition and sense a result of the stress to determine the degradation of the IC. The RAT refreshes an operation of the performance circuit if it is determined that the IC degraded before the lifetime of the IC.

An integrated circuitry includes a first logic block coupled between a first power supply terminal and a second power supply terminal. The first logic block includes a first scan chain and a configurable defect coupled to a scan output node of the first scan chain. The configurable defect has a logic node and a conductive element coupled between the logic node and the first or the second power supply terminal. The configurable defect is configured to, during a quiescent current testing mode, place a predetermined logic state on the logic node such that a current flows through the conductive element. The current can be detected by external equipment.