A testkey includes two switching circuits and two compensation circuits. The first switching circuit transmits a test signal to a first DUT when the first DUT is being tested and functions as high impedance when the first DUT is not being tested. The second switching circuit transmits the test signal to a second DUT when the second DUT is being tested and functions as high impedance when the second DUT is not being tested. When the first DUT is not being tested and the second DUT is being tested, the first compensation circuit provides first compensation current for reducing the leakage current of the first switching circuit. When the first DUT is being tested and the second DUT is not being tested, the second compensation circuit provides second compensation current for reducing the leakage current of the second switching circuit.

The present disclosure provides a method and an apparatus of testing a circuit, and a storage medium. The method of testing a circuit includes: determining a preset circuit module in a to-be-tested circuit and a preset node in the preset circuit module; inputting a test signal to an input terminal of the to-be-tested circuit according to a preset input rule, and obtaining a signal of the preset node in the preset circuit module; and determining a status of the preset circuit module based on the obtained signal of the preset node.

A logic gate system for fault insertion testing can include a logic gate module having a plurality of input pins. The plurality of input pins can include an input signal pin configured to receive an input signal, a power supply input pin configured to receive power from a power supply, and a test input pin. The logic gate module can also include an output pin connected to the input pins via one or more logic gates. The logic gate system can include a power supply line connected to the power supply input pin and the test input pin. The logic gate system can also include a zero-ohm jumper resistor disposed between the power supply input pin and the test input pin. The zero-ohm resistor can be configured to be replaced with a low ohm resistor to allow reverse driving a voltage on the test input pin. The one or more logic gates can be configured to reverse an output at the output pin when the voltage on the test input pin is reverse driven.

An integrated circuit chip includes a plurality of function blocks; a mode controller configured to convert an input signal, received from an external device through an input/output pin, into an input pattern and test mode setting data which include a plurality of bits, and to output the test mode setting data and a mode switching enable signal when a secure pattern generated therein is the same as the input pattern; and a mode setting module configured to control the plurality of function blocks to operate in a test mode according to the mode setting data, in response to the test mode switching enable signal.

A system and method are disclosed for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.

To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.

Described herein are systems and devices for testing electrical circuits. An example integrated test system includes a unit under test (UUT), a test development system operably coupled to the UUT, the test development system being configured to perform in-circuit testing (ICT) on the UUT and a functional platform brain operably coupled to the test development system and the UUT, the functional platform brain being configured to perform functional testing (FCT) on the UUT using a test sequence protocol, wherein the test sequence protocol is configured to facilitate communication between the test development system and the functional platform brain.

A testkey includes two switching circuits and two compensation circuits. The first switching circuit transmits a test signal to a first DUT when the first DUT is being tested and functions as high impedance when the first DUT is not being tested. The second switching circuit transmits the test signal to a second DUT when the second DUT is being tested and functions as high impedance when the second DUT is not being tested. When the first DUT is not being tested and the second DUT is being tested, the first compensation circuit provides first compensation current for reducing the leakage current of the first switching circuit. When the first DUT is being tested and the second DUT is not being tested, the second compensation circuit provides second compensation current for reducing the leakage current of the second switching circuit.

Examples described herein provide a wearout card and a method for using the wearout card. The wearout card generally includes a first set of connectors configured to connect the testing apparatus to a testing controller, and a second set of connectors configured to connect the testing apparatus to a device under test (DUT). The wearout card can also include a memory configured to store identifying information of the testing apparatus and a use counter indicating a number of times different DUTs have been connected to the second set of connectors.