A measurement apparatus comprising: a clock generator configured to generate a sampling clock having a longer sampling cycle than a symbol cycle in a pattern under test including a symbol with a predefined number of symbols; a sampler configured to sample, according to the sampling clock, the pattern under test that is repeatedly inputted; and a measuring section configured to measure a sampling result of the sampler according to the sampling clock of a time point corresponding to a symbol transition that becomes subject to jitter measurements in the pattern under test that is repeatedly inputted.

A semiconductor device test apparatus for improving a loss rate of a test signal in testing a device under test is provided. The semiconductor device test apparatus includes a probe interface board, a pogo block disposed on the probe interface board and electrically connected to a device under test, an equipment board disposed under the probe interface board, an alternating current (AC) controller, transferring and receiving an AC signal for performing an AC test on at least one of the device under test and the pogo block, being mounted on the equipment board, and a physical layer equalizing (PLE) board disposed between the probe interface board and the equipment board, a first equalizing circuit, decreasing loss of the AC signal, being mounted on the PLE board.

A test and measurement device includes one or more ports configured to connect to a device under test (DUT), a time domain reflectometry (TDR) source configured receive a source control signal and to produce an incident signal to be applied to the DUT, one or more analog-to-digital converters (ADC) configured to receive a sample clock and sample the incident signal from the TDR source and a time domain reflection (TDR) signal or a time domain transmission (TDT) signal from the DUT to produce an incident waveform and a TDR/TDT waveform, one or more processors configured to execute code to cause the one or more processors to: control a clock synthesizer to produce the sample clock and the source control signal, and use a period of the TDR source, a period of the sample clock, and the number of samples to determine time locations for samples in the incident waveform and the TDR/TDT waveform, and a display configured to display the incident waveform and the TDR/TDT waveform. A method of sampling a waveform using a real-equivalent-time oscilloscope having a time domain reflectometry source, comprising: controlling a clock synthesizer to produce a sample clock and a source control signal; using a time domain reflectometry (TDR) source to receive the source control signal and to produce an incident signal to be applied to a device under test (DUT); receiving the sample clock at one or more analog-to-digital converters (ADC) and sampling the incident signal from the TDR source and a TDR/TDT signal from the DUT to produce an incident waveform and a TDR/TDT waveform; determining time locations for samples in the incident waveform and the TDR/TDT waveform, using a period of the TDR source, a period of the sample clock, and a number of samples; and displaying the incident waveform and the TDR/TDT waveform.

A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

A system comprises a plurality of regions, wherein ones of the plurality of regions are partitioned from others of the plurality of regions and at least one of the plurality of regions is a region under test. The system comprises at least one noise generator configured to generate noise in at least the region under test, and at least one noise monitor configured to monitor one or more effects of the noise generated in the region under test. The system comprises a test controller configured to: cause the at least one noise generator to generate the noise in at least the region under test; receive information from the at least one noise monitor indicative of the one or more effects of the noise generated in the region under test; and determine one or more conditions based on at least a portion of the received information.

A system and method for jitter injection is provided. The system may include a serializer-deserializer (SerDes) circuit. In some examples, the serializer-deserializer (SerDes) circuit have a pre-emphasis circuit and a post emphasis circuit. The system may also include a controller, which may be used to apply specific and varying amounts of pre-emphasis and post-emphasis. The system may also include a jitter injector. In some examples, the jitter injector may be used to inject jitter into the serializer-deserializer (SerDes) circuit based on the applied pre-emphasis and post-emphasis.

A method for providing a jitter signal for modulating a switching frequency of a power switch for a power converter. The method comprising receiving a drive signal representative of the switching frequency of the power switch, detecting the switching frequency from the drive signal, determining if the switching frequency is less than a first threshold frequency, and modulating a frequency of the jitter signal in response to determining if the switching frequency is less than the first threshold frequency.

A scheme for noise floor de-embedding by identifying a link or relationship between noise floor from an oscilloscope and phase jitter impact on a toggling signal. The scheme uses phase or electrical spectrum and phase detection for noise floor recognition. The scheme de-embeds the impact from random noise and also removes deterministic noise or jitter from the oscilloscope. The scheme provides accurate jitter analysis for a circuit (e.g., clock data recovery circuit) after de-embedding noise floor for the oscilloscope.

A method of updating firmware in a chip in a stable and effective manner receives firmware outputted by a controller. The received firmware is burned into the chip. A voltage level of a controlling signal outputted by a controlling pin of the chip is latched to a certain level based on a latching signal at a first voltage level outputted by the controller. The storage medium is refreshed for making the burned firmware effective based on refresh instruction outputted by the controller. The latching signal at a second voltage level for unlatching the voltage level of the controlling signal is outputted by the controller if operations of the chip are stable. An updating operation of the chip by the method does not interrupt other operations being executed by the chip. A firmware updating apparatus and a computer readable storage medium applying the method are also disclosed.

A method of updating firmware in a chip in a stable and effective manner receives firmware outputted by a controller. The received firmware is burned into the chip. A voltage level of a controlling signal outputted by a controlling pin of the chip is latched to a certain level based on a latching signal at a first voltage level outputted by the controller. The storage medium is refreshed for making the burned firmware effective based on refresh instruction outputted by the controller. The latching signal at a second voltage level for unlatching the voltage level of the controlling signal is outputted by the controller if operations of the chip are stable. An updating operation of the chip by the method does not interrupt other operations being executed by the chip. A firmware updating apparatus and a computer readable storage medium applying the method are also disclosed.