A time error vector is determined using pairs of two closest points of input-referred noise data that straddle respective crossing times indicating when a clock signal representation crosses a threshold value, a slew rate of the clock signal representation, and the crossing times. A system filter is applied to the time error vector in the frequency domain. A first RMS value is determined indicating a jitter value present in the filtered time error vector. A raw clock signal time error vector of the clock signal under test is generated, the system filter is applied to the raw clock signal time error vector in the frequency domain, and a second RMS value indicating a jitter content of the filtered raw clock signal time error vector is determined. The second RMS value is corrected using the first RMS value to thereby generate a jitter measurement compensated for input-referred noise.

A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single pulse signal in synchronization with the respective delayed clock signals, and output sampling signals; and a count sub-circuit configured to output a count value resulting from counting a number of active sampling signals of the sampling signals.

A temporal jitter analyzer analyzes temporal jitter and includes: a time delay controller; a time delay member; a delay measurement circuit; an edge generator in communication with the time delay member and that receives the delayed primary signal from the time delay member and produces a reference signal from the delayed primary signal; a decision circuit in communication with the edge generator and that: receives the reference signal from the edge generator; receives a detector signal; and produces a raw decision signal from the detector signal such that a value of the raw decision signal depends on the reference signal; and a decision circuit readout in communication with the edge generator and the decision circuit and that: receives the reference signal from the edge generator; receives the raw decision signal from the decision circuit; and produces a decision signal from the raw decision signal based on the reference signal.

A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.

A jitter determination method for determining at least one jitter component of an input signal is described. The input signal is generated by a signal source. The jitter determination method includes: receiving the input signal; determining a step response based on the input signal, the step response being associated with at least the signal source; and determining at least one variation parameter associated with the determined step response, wherein the at least one variation parameter is indicative of a reliability of the determined step response. Further, a measurement instrument is described.

In a particular implementation, a method to reduce noise/clock jitter and to generate a “stretched” output clock to optimize for jitter of the output clock is disclosed. The method includes: generating two or more clock phases upon detecting a transient voltage by a detector circuit, generating an output clock signal based on one of the two or more clock phases; and altering a phase speed of the output clock signal to correspond to a phase speed of an input clock signal.

An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

A method for recovering data included in a digitally modulated signal is described. The digitally modulated signal includes a symbol sequence. The method includes providing a mathematical model of the digitally modulated signal, the mathematical model describing the digitally modulated signal in terms of the symbol sequence and describing the digitally modulated signal in terms of a step response and/or an impulse response, and wherein the mathematical model also takes disturbances into account; and processing the digitally modulated signal based on the mathematical model, thereby recovering the data included in the digitally modulated signal. The disturbances include a random disturbance component modelled as a Gaussian disturbance, and include an inter-symbol interference component modelled as Gaussian noise, and wherein a dependence of the at least one step response on the symbol sequence is neglected within the mathematical model. Further, a measurement instrument and a measurement system are described.

An apparatus and method for analyzing phase noise in a signal. A plurality of signal samples, each signal sample representing a value of phase noise in a signal-under-test at a corresponding offset frequency, and filter data representing filter characteristics on a first side of a spectrum boundary, are used to derive filtered signal samples. A measure of noise is derived from the filtered signal samples. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.