An embodiment of a method for operating a modular test bench is disclosed, wherein the modular test bench comprises at least one test module to test a test object. The method comprises receiving first information on a hardware revision and on a software revision of the test module and receiving second information on a hardware revision and on a software revision of the test object. The method further comprises determining, if the combination of the first information and the second information fulfills a predetermined criterion and outputting a check signal, enabling the use of the test bench if the combination of the first information and the second information fulfills the predetermined criterion.

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Power-glitch detection and power-glitch self-testing within a chip is shown. In a chip, a processor has a power terminal, a glitch detector, and a self-testing circuit. The power terminal is configured to receive power. The glitch detector is coupled to the power terminal of the processor for power-glitch detection. The self-testing circuit has a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector.

A non-transitory computer-readable recording medium stores an analysis program for causing a computer to execute a process including: reading circuit data; trying to generate test data for a delay fault to be targeted; analyzing whether an underkill is caused when the targeted delay fault results in a redundant fault; and presenting circuit modification locations to avoid the underkill, based on an analysis result, when the underkill is caused.

The invention relates to a method, an apparatus and a non-transitory computer-readable storage medium for debugging a solid-state disk (SSD) device. The method is performed by a processing unit of a single-board personal computer (PC) when loading and executing a function of a runtime library, to include: receiving a request to drive a General-Purpose Input/Output (GPIO) interface (I/F), which includes a parameter required for completing a Joint Test Action Group (JTAG) command; issuing a first hardware instruction to the GPIO I/F to set a register corresponding to a GPIO test data input (TDI) pin according to the parameter carried in the request for emulating to issue the JTAG command to a solid-state disk (SSD) device, wherein the single-board PC is coupled to the SSD device through the GPIO I/F; issuing a second hardware instruction to the GPIO I/F to read a value of the register corresponding to the GPIO TDI pin; and replying with a completion message in response to the request.

The present invention relates to a device (1) such as a connected object comprising a first electronic circuit (2) comprising: a first processing unit (6) for executing a program, a first memory (8) for memorizing data during the execution of the program, a debug port (10) dedicated to checking the execution of the program from outside the first circuit,
a second electronic circuit (4) connected to the debug port (10), comprising: a second memory (14) memorizing reference data related to the program, a second processing unit (12) for implementing the following steps automatically and autonomously via the debug port (10): checking the integrity of the data memorized by the first memory (8) and/or the compliance of the program's execution by the first processing unit (6) with a reference execution, assisted by the reference data.

A voltage monitoring circuit is disclosed. An apparatus includes a first physical interface circuit and a real-time oscilloscope circuit configured to monitor a first voltage provided to the first physical interface circuit. The real-time oscilloscope is configured to receive an indication that an error was detected in data transmitted from the first physical interface to a second physical interface circuit. The real-time oscilloscope is further configured to provide for debug, to a host computer external to the first interface, information indicating a state of the first voltage at a time at which the error was detected.

An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes a first processor configured to execute a custom BMC firmware stack, and a second processor including executable instructions for receiving a request to perform a test on the first processor in which the request is received through a secure communication session established with a remote IHS. The instructions further perform the acts of controlling the first processor to perform the test according to the request, the first processor generating test results associated with the test, and transmitting the test results to the remote IHS through the secure communication session.

A non-transitory computer-readable recording medium stores an analysis program for causing a computer to execute a process including: reading circuit data; trying to generate test data for a delay fault to be targeted; analyzing whether an underkill is caused when the targeted delay fault results in a redundant fault; and presenting circuit modification locations to avoid the underkill, based on an analysis result, when the underkill is caused.