Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

The present disclosure relates to self-test circuitry for a system that includes one or more current control subsystems, each current control subsystem having a load terminal for coupling the current control subsystem to a load. The self-test circuitry comprises: a signal path associated with each current control subsystem, each signal path configured to selectively couple a measurement node to the load terminal of the current control subsystem, wherein the measurement node is common to all of the signal paths; voltage detection circuitry; and test voltage source circuitry configured to provide a test voltage to the measurement node. The voltage detection circuitry is operable to output a signal indicative of a fault condition if a voltage detected at the measurement node differs from the test voltage when the measurement node is coupled to the load terminal.

The present invention discloses a hysteresis signal detection circuit, comprising: a first MOS transistor, a second MOS transistor, an inverter INV1, an inverter INV2 and an inverter INV3. A gate of the first MOS transistor is connected with an input end, and a drain of the first MOS transistor is connected with an output end through the inverter INV1, the inverter INV2 and the inverter INV3 successively; a source of the first MOS transistor is connected with a drain of the second MOS transistor, and a gate of the second MOS transistor is connected between the inverter INV1 and the inverter INV2; and a resistor R1 is connected between a source and the drain of the second MOS transistor. In the present invention, not only the hysteresis voltage can be adjusted through current and resistance values, which is flexible, but also the hysteresis voltage may not change with power voltage.

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die module coupled to the package substrate. In an embodiment, the die module comprises a die and a chiplet coupled to the die. In an embodiment, the chiplet is coupled to the die with a hybrid bonding interconnect architecture.

Testing of at least one source by a destination is provided, which comprises: (i) the destination supplies a test signal towards the at least one source; (ii) at the at least one source, determining a second output signal based on a first output signal and the test signal via a first function; (iii) conveying the second output signal to the destination; (iv) at the destination, determining a received signal based on the second output signal received from the at least one source and based on the test signal via a second function; and (v) determining whether an error occurred based on the received signal. Also, an according system is provided.

A method and a system are disclosed for determining health of a web application. The method includes receiving data for parameters related to exceptions, network anomalies, resource performance, and user experience, associated with devices and servers in the IT environment. A score is determined for the parameters and compared in a multiple-rating scale to obtain parameter ratings for the parameters. A final rating for the exceptions, network anomalies, resource performance, and user experience are determined based on the parameter ratings. The determined final ratings are used for automatically generating an application health index. The application health index provides an accurate and near real-time indication of the health of an application by considering various parameters for each network node in the IT environment.

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

The present disclosure provides a method of testing a single device under test (DUT) through multiple cores in parallel, which includes steps as follows. The test quantity of the DUT is calculated; the test quantity of the DUT is evenly allocated to to a plurality of test cores, so as to control a period of testing the DUT through the test cores in parallel.

A testing system includes a subtractor and a divider. The subtractor is configured to receive a first voltage of a circuit being tested and a second voltage of the circuit, and to derive a difference between the first voltage and the second voltage. The divider is configured to receive the difference between the first voltage and the second voltage, and to derive a resistance of the circuit by dividing (i) the difference between the first voltage and the second voltage by (ii) a difference between a first current applied to the circuit and a second current applied to the circuit. The first voltage is corresponding to the first current, and the second voltage is corresponding to the second current.