An integrated circuit includes first to n.sup.th metal layers vertically stacked on a substrate, and a test circuit outputting a test result signal according to a characteristic of each of the first to n.sup.th metal layers. The test circuit includes first to n.sup.th test circuits for generating a plurality of clock signals. Each clock signal of the plurality of clock signal has a frequency according to a characteristic of a corresponding metal layer among the first to n.sup.th metal layers, and n is a natural number.

A test method for a delay circuit and a test circuitry are provided. The test circuitry incudes the delay circuit that essentially includes multiple serially connected logic gates, a clock pulse generator at an input end of the delay circuit for generating one or more cycles of clock signals, and a counter at an output end of the delay circuit for counting the clock signals passing through the delay circuit. The test circuitry implements a test mode by switching lines to the clock pulse generator and the counter. The test circuitry relies on a comparison result of a counting result made by the counter and a number of the cycles of the clock signals to test any failure of the delay circuit.

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

A first clock signal and second clock signal are generated by first and second clock circuits, respectively. A multiplexer selects between the first clock signal and second clock signal to produce a scan clock signal. A non-scan flip flop clocks a data input through to a data output in response to the second clock signal. A scan chain includes a scan flip flop configured to capture the data output from the non-scan flip flop in response to the scan clock signal. The logic state of the captured data in the scan flip flop of the scan chain is indicative of whether the second clock circuit has a stuck-at fault condition (for example, with respect to any one or more included buffer circuits).

A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

A temporal jitter analyzer analyzes temporal jitter and includes: a time delay controller; a time delay member; a delay measurement circuit; an edge generator in communication with the time delay member and that receives the delayed primary signal from the time delay member and produces a reference signal from the delayed primary signal; a decision circuit in communication with the edge generator and that: receives the reference signal from the edge generator; receives a detector signal; and produces a raw decision signal from the detector signal such that a value of the raw decision signal depends on the reference signal; and a decision circuit readout in communication with the edge generator and the decision circuit and that: receives the reference signal from the edge generator; receives the raw decision signal from the decision circuit; and produces a decision signal from the raw decision signal based on the reference signal.

A detection circuit for detecting a clock signal includes a multiplexer, a digital-to-analog converter, a comparator, and a counter. The multiplexer outputs either a first signal or a second signal as a selection signal. The digital-to-analog converter outputs a reference voltage according to the selection signal. The comparator compares the clock signal to the reference voltage to generate a comparison signal. The counter counts a reference clock signal to generate an overflow signal, and resets the overflow signal according to the comparison signal. The overflow signal indicates the amplitude of the clock signal.

The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Embodiments of the present application provide a time offset method and device for a test signal. When a signal source sends a test signal to a DUT on a test platform, the offset device can determine a time delay caused by impedance matching of the test signal to the DUT at the upper side of each test location, and conduct time offset for TCK signals sent by the signal source to different DUTs according to the time delay.