An integrated circuit (IC) test engine can generate a plurality of single cycle test patterns that target a plurality of static single cycle defects of a fabricated IC chip based on an IC design. The IC test engine can also fault simulate the plurality of single cycle test patterns against a plurality of multicycle defects in the IC design, wherein a given single cycle test pattern of the plurality of single cycle test patterns is sim-shifted to enable detection of a given multicycle fault and/or defect of the plurality of multicycle faults and/or defects.

An exemplary method of detecting a Trojan circuit in an integrated circuit is related to applying a test pattern comprising an initial test pattern followed by a corresponding succeeding test pattern to a golden design of the integrated circuit, wherein a change in the test pattern increases side-channel sensitivity; measuring a side-channel parameter in the golden design of the integrated circuit after application of the test pattern; applying the test pattern to a design of the integrated circuit under test; measuring the side-channel parameter in the design of the integrated circuit under test after application of the test pattern; and determining a Trojan circuit to be present in the integrated circuit under test when the measured side-channel parameters vary by a threshold.

An apparatus includes a core logic circuit, one or more integrated clock-gating (ICG) cells, and one or more ICG control cells (ICCs). The core logic circuit generally comprises a plurality of flip-flops. The plurality of flip-flops may be connected to form one or more scan chains. Each of the one or more integrated clock-gating (ICG) cells may be configured to gate a clock signal of a respective one of the one or more scan chains. Each of the one or more ICG control cells may be configured to control a respective one or more of the one or more ICG cells.

Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.

A power electronic circuit fault diagnosis method based on Extremely randomized trees (ET) and Stack Sparse auto-encoder (SSAE) algorithm includes the following. First, collect the fault signal and extract fault features. Then, reduce the dimensionality of fault features by calculating the importance value of all features using ET algorithm. A proportion of the features to be eliminated is determined, and a new feature set is obtained according the value of importance. Further extraction of fault features is carried by using SSAE algorithm, and hidden layer features of the last sparse auto-encoder are obtained as fault features after dimensionality reduction. Finally, the fault samples in a training set and a test set are input to the classifier for training to obtain a trained classifier. And mode identification, wherein the fault of the power electronic circuit is identified and located by the training classifier.

The signal toggling detection and correction circuit includes a flip-flop, a checker circuit, and a fault monitoring circuit that includes a restoration circuit. Based on faults such as soft errors and unintended bit toggles in the flip-flop, a flop output signal toggles. A set of checker signals outputted by the checker circuit may toggle based on toggling of the flop output signal and a restoration signal of the restoration circuit. Based on the toggling of at least one checker signal, the fault monitoring circuit determines whether the flip-flop or the checker circuit is faulty. When the checker circuit is faulty, the fault monitoring circuit corrects the toggling of at least one checker signal. When the flip-flop is faulty, the fault monitoring circuit corrects the toggling of one of the toggled flop output signal or the restoration signal and further corrects the toggled checker signal.

A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.

Systems and methods disclosed include receiving defect data from a test of a semiconductor device comprising a circuit, the circuit comprising a cell, the cell comprising a first input, a second input and an output, and modeling a first plurality of cell defect modes of the cell with a first multiple input transition cell fault model (MTCFM), the cell defect modes associated with a first signal transition on the first input, and a second signal transition on the second input or the output. Systems and method further include correlating the first plurality of cell defect modes to the defect data to produce a probability of each of the first plurality of cell defect modes matching the defect data, and providing, to a user, an indication of each of at least one of the first plurality of cell defect modes having the probability exceeding a defect probability threshold.

A method for testing circuit elements at one or more manufacturing stages comprising receiving, at a circuit verifier a fingerprint of at least a circuit element to be manufactured, wherein the fingerprint further comprises at least an expected output corresponding to at least a test input, transmitting, from the circuit verifier the at least a test input to the at least a circuit element, receiving, at the circuit verifier at least a test output from the at least a circuit element, and comparing, by the circuit verifier the at least a test output to the at least an expected output of the fingerprint of the at least a circuit element.

Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.