A system for testing a circuit comprises scan chains, a controller configured to generate a bit-inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation. Here, the plurality of shift clock cycles for bit inverting occur every m shift clock cycles, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles in the shift operation.

A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.

A method for recovering data included in a digitally modulated signal is described. The digitally modulated signal includes a symbol sequence. The method includes providing a mathematical model of the digitally modulated signal, the mathematical model describing the digitally modulated signal in terms of the symbol sequence and describing the digitally modulated signal in terms of a step response and/or an impulse response, and wherein the mathematical model also takes disturbances into account; and processing the digitally modulated signal based on the mathematical model, thereby recovering the data included in the digitally modulated signal. The disturbances include a random disturbance component modelled as a Gaussian disturbance, and include an inter-symbol interference component modelled as Gaussian noise, and wherein a dependence of the at least one step response on the symbol sequence is neglected within the mathematical model. Further, a measurement instrument and a measurement system are described.

A test and measurement system includes a test and measurement device configured to receive a signal from a device under test, and one or more processors configured to execute code that causes the one or more processors to generate a waveform from the signal, apply an equalizer to the waveform, receive an input identifying one or more measurements to be made on the waveform, select a number of unit intervals (UIs) for a known data pattern, scan the waveform for the known data patterns having a length of the number of UIs, identify the known data patterns as short pattern waveforms, apply a machine learning system to the short pattern waveforms to obtain a value for the one or more measurements, and provide the values of the one or more measurements for the waveform. A method includes receiving a signal from a device under test, generating a waveform from the signal, applying an equalizer to the waveform, receiving an input identifying one or more measurements to be made on the waveform, selecting a number of unit intervals (UIs), scanning the waveform to identify short pattern waveforms having a length equal to the number of UIs, applying a machine learning system to the short pattern waveforms to obtain a value for the one or more measurements, and providing the values of the one or more measurements for the waveform from the machine learning system.

A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.

One embodiment provides a method and a system for generating test vectors for testing a computational system. During operation, the system obtains a design of the computational system, the design comprising an original system. The system generates a design of a fault-augmented system block by adding a plurality of fault-emulating subsystems to the original system; generates a design of an equivalence-checking system based on the original system and the fault-augmented system block; encodes the design of the equivalence-checking system into a logic formula, with variables within the logic formula comprising inputs and outputs of the original system and inputs and outputs of the fault-augmented system block; and solves the logic formula to obtain a test vector used for testing at least one fault in the computational system.

Embodiments of the present invention, which relate to the field of electronic technologies, provide a monitoring method, a monitoring apparatus, and an electronic device, which can accurately locate an error point in MPI information delivered by a system chip. The apparatus may include: an address filter, a read/write controller connected to the address filter, and a memory connected to the read/write controller, where the address filter is configured to acquire multiple pieces of MPI information, and obtain, by filtering the multiple pieces of MPI information, first MPI information corresponding to a first service that is preset; the read/write controller is configured to write, into the memory according to a time sequence of receiving the first MPI information, the first MPI information that is obtained by the address filter by filtering; and the memory is configured to store the first MPI information written by the read/write controller.

Disclosed is a semiconductor integrated circuit including a logic circuit, and a plurality of scan flip-flop circuits that hold input data or output data of the logic circuit and are capable of forming a scan chain for executing a scan test of the logic circuit. Each scan flip-flop circuit includes a scan data input part that receives input of scan data for the scan test, a normal data input part that receives input of normal data different from the scan data, and a data holding part capable of separately holding the normal data and the scan data.

A semiconductor device includes a scan input circuit, a master latch, a slave latch, a first inverter, and a scan output circuit. The scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal. The master latch is configured to latch the first select signal and output a first output signal. The slave latch is configured to latch the first output signal and output a second output signal. The first inverter is configured to invert the second output signal. The scan output circuit is configured to receive a signal output from the slave latch and an external signal and output a first scan output signal.

Methods and apparatuses to assign faults to nets in an integrated circuit (IC) are described. Each net comprises a drive pin, a set of load pins, and a fan-out structure that electrically couples the drive pin to the set of load pins. During operation, a fan-out structure of a net can be partitioned into a set of non-overlapping subnets and a set of branch nodes, wherein each branch node electrically couples three or more non-overlapping subnets. Next, each branch node can be represented by using a subnet primitive, wherein each subnet primitive comprises three or more pins that are electrically coupled to non-overlapping subnets that are electrically coupled by the branch node. A fault can then be assigned to a pin of a subnet primitive that is electrically coupled to a non-overlapping subnet, thereby modeling the fault in the non-overlapping subnet.