A semiconductor device test apparatus for improving a loss rate of a test signal in testing a device under test is provided. The semiconductor device test apparatus includes a probe interface board, a pogo block disposed on the probe interface board and electrically connected to a device under test, an equipment board disposed under the probe interface board, an alternating current (AC) controller, transferring and receiving an AC signal for performing an AC test on at least one of the device under test and the pogo block, being mounted on the equipment board, and a physical layer equalizing (PLE) board disposed between the probe interface board and the equipment board, a first equalizing circuit, decreasing loss of the AC signal, being mounted on the PLE board.

This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.

A signal generator and a method for controlling the signal generator, capable of suppressing variation in the intensity of signals inputted to multiple devices under test are provided. An attenuation amount setting unit 15 sets a reference attenuation amount, obtained by subtracting the maximum amount of the losses stored in the cable loss storage unit 16 with respect to the cables 4a to 4f connected to the output ports 12a to 12f from a target attenuation amount, to the first attenuator 11, and sets an output attenuation amount, obtained by subtracting the losses stored in the cable loss storage unit 16 with respect to each of the cables 4a to 4f connected to the output ports 12a to 12f, from the maximum amount of the losses, to each of the second attenuators 14a to 14f.

This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

Systems, methods, and computer program products directed to testing a System-in-a-Package (SIP) using an Automatic Test Equipment (ATE) machine. A functional representation of one or more tests to be performed in the SIP is loaded in a memory located on a load board, the load board located on the ATE machine. A test controller located on at least one of the SIP and the load board is caused to retrieve and store the one or more tests to be performed in the SIP. The test controller is instructed to conduct the one or more tests in the SIP.

A signal generator and a method for controlling the signal generator, capable of suppressing variation in the intensity of signals inputted to multiple devices under test are provided. An attenuation amount setting unit 15 sets a reference attenuation amount, obtained by subtracting the maximum amount of the losses stored in the cable loss storage unit 16 with respect to the cables 4a to 4f connected to the output ports 12a to 12f from a target attenuation amount, to the first attenuator 11, and sets an output attenuation amount, obtained by subtracting the losses stored in the cable loss storage unit 16 with respect to each of the cables 4a to 4f connected to the output ports 12a to 12f, from the maximum amount of the losses, to each of the second attenuators 14a to 14f.

This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.