According to an embodiment of the present disclosure, a semiconductor memory device includes a mode register circuit including a plurality of write mode register sets for providing a plurality of setting codes or a plurality of monitoring codes; and a defect detection circuit suitable for outputting a defect determination signal by detecting any defect in the mode register circuit, based on the plurality of monitoring codes, wherein each of the write mode register sets includes: a storing circuit suitable for storing an operational code according to a mode register write command; and an output control circuit suitable for outputting the stored operational code in the storing circuit as a corresponding setting code, or inverting the stored operational code in the storing circuit to output a corresponding monitoring code, according to a test mode signal.

An apparatus that allows for access to any and all registers of a central processing unit in a line replaceable unit (LRU) without a need to open the housing of the LRU is provided. The apparatus may receive write or read packets from an external device and relay the same to an LRU. The apparatus may receive state information from one or more registers of the LRU in response. The apparatus may transmit or transfer the state information to an external device. The apparatus may be used to update firmware in the LRU, for diagnostics or testing.

According to an embodiment of the present disclosure, a semiconductor memory device includes a mode register circuit including a plurality of write mode register sets for providing a plurality of setting codes or a plurality of monitoring codes; and a defect detection circuit suitable for outputting a defect determination signal by detecting any defect in the mode register circuit, based on the plurality of monitoring codes, wherein each of the write mode register sets includes: a storing circuit suitable for storing an operational code according to a mode register write command; and an output control circuit suitable for outputting the stored operational code in the storing circuit as a corresponding setting code, or inverting the stored operational code in the storing circuit to output a corresponding monitoring code, according to a test mode signal.

A method for testing a chip comprising: receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.

A method for testing a chip comprising receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.

A circuit, including a TAP circuit, a routing circuit, a first test path and a second test path, is provided. A first input terminal and a first output terminal of the routing circuit are respectively coupled to a scan output terminal and a first scan input terminal of the TAP circuit. A first terminal of the first test path is coupled to a second input terminal of the routing circuit. A second terminal of the first test path is coupled to a second output terminal of the routing circuit. A first terminal of the second test path is coupled to a third input terminal of the routing circuit. A second terminal of the second test path is coupled to a third output terminal of the routing circuit. The routing circuit couples the scan output terminal of the TAP circuit to the first scan input terminal of the TAP circuit or the first terminal of the first test path or the first terminal of the second test path.

A circuit, including a TAP circuit, a routing circuit, a first test path and a second test path, is provided. A first input terminal and a first output terminal of the routing circuit are respectively coupled to a scan output terminal and a first scan input terminal of the TAP circuit. A first terminal of the first test path is coupled to a second input terminal of the routing circuit. A second terminal of the first test path is coupled to a second output terminal of the routing circuit. A first terminal of the second test path is coupled to a third input terminal of the routing circuit. A second terminal of the second test path is coupled to a third output terminal of the routing circuit. The routing circuit couples the scan output terminal of the TAP circuit to the first scan input terminal of the TAP circuit or the first terminal of the first test path or the first terminal of the second test path.

A method includes providing a first and second electronic unit unit, generating a wirelessly transmitted signal for detecting or generating one signal or several signals for detection on a chain of electronic elements, for the first unit, detecting a transmission time of the wirelessly transmitted signal for detection or detecting a first transmission time on a first of the chain, for the second unit, detecting a second value or the transmission time of the wirelessly transmitted signal for detection or detecting a second value or a second transmission time on a second position of the chain that is different from the first position, converting the first value or the transmission time detected for the first unit to a first address for the first unit, and converting the second value or the transmission time detected within or for the second unit to a second address for the second unit.

A method includes providing a first and second electronic unit unit, generating a wirelessly transmitted signal for detecting or generating one signal or several signals for detection on a chain of electronic elements, for the first unit, detecting a transmission time of the wirelessly transmitted signal for detection or detecting a first transmission time on a first of the chain, for the second unit, detecting a second value or the transmission time of the wirelessly transmitted signal for detection or detecting a second value or a second transmission time on a second position of the chain that is different from the first position, converting the first value or the transmission time detected for the first unit to a first address for the first unit, and converting the second value or the transmission time detected for the second unit to a second address for the second unit.

Testing systems and method of testing an integrated circuit are provided. A testing system comprises an input terminal, multiple circuit elements, each having a register, and an output terminal forming a scan chain through which an input signal is propagated. The testing system further comprises a debugger that includes a mapping module that stores information mapping register values to their respective functional meanings. The input signal is applied to extract all values of all of the registers whether or not accessible by a processor.