An apparatus includes a core logic circuit, one or more integrated clock-gating (ICG) cells, and one or more ICG control cells (ICCs). The core logic circuit generally comprises a plurality of flip-flops. The plurality of flip-flops may be connected to form one or more scan chains. Each of the one or more integrated clock-gating (ICG) cells may be configured to gate a clock signal of a respective one of the one or more scan chains. Each of the one or more ICG control cells may be configured to control a respective one or more of the one or more ICG cells.

A first clock signal and second clock signal are generated by first and second clock circuits, respectively. A multiplexer selects between the first clock signal and second clock signal to produce a scan clock signal. A non-scan flip flop clocks a data input through to a data output in response to the second clock signal. A scan chain includes a scan flip flop configured to capture the data output from the non-scan flip flop in response to the scan clock signal. The logic state of the captured data in the scan flip flop of the scan chain is indicative of whether the second clock circuit has a stuck-at fault condition (for example, with respect to any one or more included buffer circuits).

A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

The present application discloses a calibration data generation circuit and an associated method. The calibration data generation circuit includes: a first delay unit, having a first delay amount; and a first scan path, including: a first scan flip-flop, including: a scan data input terminal; a clock input terminal, arranged for receiving a clock signal; and an output terminal; and a second scan flip-flop, including: a scan data input terminal, coupled to the output terminal of the first scan flip-flop; a clock input terminal, arranged for receiving a delayed clock signal formed by the clock signal passing through the first delay unit; and an output terminal; wherein when the calibration data generation circuit operates, the first scan flip-flop and the second scan flip-flop are configured in a scan shift mode.

The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.

The signal toggling detection and correction circuit includes a flip-flop, a checker circuit, and a fault monitoring circuit that includes a restoration circuit. Based on faults such as soft errors and unintended bit toggles in the flip-flop, a flop output signal toggles. A set of checker signals outputted by the checker circuit may toggle based on toggling of the flop output signal and a restoration signal of the restoration circuit. Based on the toggling of at least one checker signal, the fault monitoring circuit determines whether the flip-flop or the checker circuit is faulty. When the checker circuit is faulty, the fault monitoring circuit corrects the toggling of at least one checker signal. When the flip-flop is faulty, the fault monitoring circuit corrects the toggling of one of the toggled flop output signal or the restoration signal and further corrects the toggled checker signal.

A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

A semiconductor integrated circuit includes scan chains, each of which includes a serial connection of sequential circuits and performs a shift register operation in a scan test; and an integrated clock gating (ICG) chain composed by coupling, to one another, ICG circuits, each of which individually supplies a corresponding one of the scan chains with a circuit clock signal to operate the sequential circuits. In the ICG chain, an ICG enable propagation signal for controlling timing when the ICG circuits output the circuit clock signals propagates through a signal line and is input sequentially to the ICG circuits. The ICG circuits output the circuit clock signals at respective timings that are different among the scan chains.

A semiconductor device comprises a plurality of memory elements, test control circuitry, and a testing interface. The test control circuitry is configure to determine that one or more clock signals associated with the memory elements have been stopped and generate a scan clock signal based on the determination that the one or more clock signals have been stopped. The test control circuitry is further configured to communicate the scan clock signal to the memory elements. The testing interface is configured to communicate test data from the memory elements. In one example, the test data is delimited with start and end marker elements. The semiconductor device is mounted to a circuit board and is communicatively coupled to communication pins of the circuit board.